diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 31 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm206/bios_gm206.c | 4 |
3 files changed, 27 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 9a51e11c..339e53b2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -64,6 +64,12 @@ | |||
64 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 | 64 | #define NV_PERF_PMM_FBP_ROUTER_STRIDE 0x0200 |
65 | #define NV_PERF_PMMGPC_CHIPLET_OFFSET 0x1000 | 65 | #define NV_PERF_PMMGPC_CHIPLET_OFFSET 0x1000 |
66 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 | 66 | #define NV_PERF_PMMGPCROUTER_STRIDE 0x0200 |
67 | #define FE_PWR_MODE_TIMEOUT_MAX 2000 | ||
68 | #define FE_PWR_MODE_TIMEOUT_DEFAULT 10 | ||
69 | #define CTXSW_MEM_SCRUBBING_TIMEOUT_MAX 1000 | ||
70 | #define CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
71 | #define FECS_ARB_CMD_TIMEOUT_MAX 40 | ||
72 | #define FECS_ARB_CMD_TIMEOUT_DEFAULT 2 | ||
67 | 73 | ||
68 | static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g); | 74 | static int gk20a_init_gr_bind_fecs_elpg(struct gk20a *g); |
69 | static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 75 | static int gr_gk20a_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
@@ -1523,7 +1529,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1523 | unsigned long end_jiffies = jiffies + | 1529 | unsigned long end_jiffies = jiffies + |
1524 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | 1530 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); |
1525 | u32 last_method_data = 0; | 1531 | u32 last_method_data = 0; |
1526 | int retries = 200; | 1532 | int retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; |
1527 | 1533 | ||
1528 | gk20a_dbg_fn(""); | 1534 | gk20a_dbg_fn(""); |
1529 | 1535 | ||
@@ -1542,7 +1548,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1542 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1548 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1543 | if (req == gr_fe_pwr_mode_req_done_v()) | 1549 | if (req == gr_fe_pwr_mode_req_done_v()) |
1544 | break; | 1550 | break; |
1545 | udelay(GR_IDLE_CHECK_DEFAULT); | 1551 | udelay(FE_PWR_MODE_TIMEOUT_MAX); |
1546 | } while (--retries || !tegra_platform_is_silicon()); | 1552 | } while (--retries || !tegra_platform_is_silicon()); |
1547 | } | 1553 | } |
1548 | 1554 | ||
@@ -1579,12 +1585,12 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1579 | gk20a_writel(g, gr_fe_pwr_mode_r(), | 1585 | gk20a_writel(g, gr_fe_pwr_mode_r(), |
1580 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); | 1586 | gr_fe_pwr_mode_req_send_f() | gr_fe_pwr_mode_mode_auto_f()); |
1581 | 1587 | ||
1582 | retries = 200; | 1588 | retries = FE_PWR_MODE_TIMEOUT_MAX / FE_PWR_MODE_TIMEOUT_DEFAULT; |
1583 | do { | 1589 | do { |
1584 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); | 1590 | u32 req = gr_fe_pwr_mode_req_v(gk20a_readl(g, gr_fe_pwr_mode_r())); |
1585 | if (req == gr_fe_pwr_mode_req_done_v()) | 1591 | if (req == gr_fe_pwr_mode_req_done_v()) |
1586 | break; | 1592 | break; |
1587 | udelay(GR_IDLE_CHECK_DEFAULT); | 1593 | udelay(FE_PWR_MODE_TIMEOUT_DEFAULT); |
1588 | } while (--retries || !tegra_platform_is_silicon()); | 1594 | } while (--retries || !tegra_platform_is_silicon()); |
1589 | 1595 | ||
1590 | if (!retries) | 1596 | if (!retries) |
@@ -2230,13 +2236,13 @@ int gr_gk20a_init_ctxsw_ucode(struct gk20a *g) | |||
2230 | void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | 2236 | void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) |
2231 | { | 2237 | { |
2232 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; | 2238 | struct gk20a_ctxsw_ucode_info *ucode_info = &g->ctxsw_ucode_info; |
2233 | int retries = 20; | 2239 | int retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2234 | phys_addr_t inst_ptr; | 2240 | phys_addr_t inst_ptr; |
2235 | u32 val; | 2241 | u32 val; |
2236 | 2242 | ||
2237 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & | 2243 | while ((gk20a_readl(g, gr_fecs_ctxsw_status_1_r()) & |
2238 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { | 2244 | gr_fecs_ctxsw_status_1_arb_busy_m()) && retries) { |
2239 | udelay(2); | 2245 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2240 | retries--; | 2246 | retries--; |
2241 | } | 2247 | } |
2242 | if (!retries) { | 2248 | if (!retries) { |
@@ -2260,10 +2266,10 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2260 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); | 2266 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), 0x7); |
2261 | 2267 | ||
2262 | /* Wait for arbiter command to complete */ | 2268 | /* Wait for arbiter command to complete */ |
2263 | retries = 20; | 2269 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2264 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2270 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2265 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | 2271 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { |
2266 | udelay(2); | 2272 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2267 | retries--; | 2273 | retries--; |
2268 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2274 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2269 | } | 2275 | } |
@@ -2277,10 +2283,10 @@ void gr_gk20a_load_falcon_bind_instblk(struct gk20a *g) | |||
2277 | /* Send command to arbiter to flush */ | 2283 | /* Send command to arbiter to flush */ |
2278 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), gr_fecs_arb_ctx_cmd_cmd_s()); | 2284 | gk20a_writel(g, gr_fecs_arb_ctx_cmd_r(), gr_fecs_arb_ctx_cmd_cmd_s()); |
2279 | 2285 | ||
2280 | retries = 20; | 2286 | retries = FECS_ARB_CMD_TIMEOUT_MAX / FECS_ARB_CMD_TIMEOUT_DEFAULT; |
2281 | val = (gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); | 2287 | val = (gk20a_readl(g, gr_fecs_arb_ctx_cmd_r())); |
2282 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { | 2288 | while (gr_fecs_arb_ctx_cmd_cmd_v(val) && retries) { |
2283 | udelay(2); | 2289 | udelay(FECS_ARB_CMD_TIMEOUT_DEFAULT); |
2284 | retries--; | 2290 | retries--; |
2285 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); | 2291 | val = gk20a_readl(g, gr_fecs_arb_ctx_cmd_r()); |
2286 | } | 2292 | } |
@@ -4742,7 +4748,8 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4742 | 4748 | ||
4743 | static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | 4749 | static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) |
4744 | { | 4750 | { |
4745 | int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT; | 4751 | int retries = CTXSW_MEM_SCRUBBING_TIMEOUT_MAX / |
4752 | CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT; | ||
4746 | bool fecs_scrubbing; | 4753 | bool fecs_scrubbing; |
4747 | bool gpccs_scrubbing; | 4754 | bool gpccs_scrubbing; |
4748 | 4755 | ||
@@ -4762,7 +4769,7 @@ static int gr_gk20a_wait_mem_scrubbing(struct gk20a *g) | |||
4762 | return 0; | 4769 | return 0; |
4763 | } | 4770 | } |
4764 | 4771 | ||
4765 | udelay(GR_IDLE_CHECK_DEFAULT); | 4772 | udelay(CTXSW_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
4766 | } while (--retries || !tegra_platform_is_silicon()); | 4773 | } while (--retries || !tegra_platform_is_silicon()); |
4767 | 4774 | ||
4768 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); | 4775 | gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout"); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index b60d1b71..8ce7f32d 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -37,6 +37,9 @@ | |||
37 | 37 | ||
38 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" | 38 | #define GK20A_PMU_UCODE_IMAGE "gpmu_ucode.bin" |
39 | 39 | ||
40 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | ||
41 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | ||
42 | |||
40 | #define gk20a_dbg_pmu(fmt, arg...) \ | 43 | #define gk20a_dbg_pmu(fmt, arg...) \ |
41 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | 44 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) |
42 | 45 | ||
@@ -2119,7 +2122,8 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2119 | gk20a_dbg_fn(""); | 2122 | gk20a_dbg_fn(""); |
2120 | 2123 | ||
2121 | if (enable) { | 2124 | if (enable) { |
2122 | int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT; | 2125 | int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX / |
2126 | PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT; | ||
2123 | gk20a_enable(g, mc_enable_pwr_enabled_f()); | 2127 | gk20a_enable(g, mc_enable_pwr_enabled_f()); |
2124 | 2128 | ||
2125 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) | 2129 | if (g->ops.clock_gating.slcg_pmu_load_gating_prod) |
@@ -2138,7 +2142,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable) | |||
2138 | gk20a_dbg_fn("done"); | 2142 | gk20a_dbg_fn("done"); |
2139 | return 0; | 2143 | return 0; |
2140 | } | 2144 | } |
2141 | udelay(GR_IDLE_CHECK_DEFAULT); | 2145 | udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT); |
2142 | } while (--retries || !tegra_platform_is_silicon()); | 2146 | } while (--retries || !tegra_platform_is_silicon()); |
2143 | 2147 | ||
2144 | gk20a_disable(g, mc_enable_pwr_enabled_f()); | 2148 | gk20a_disable(g, mc_enable_pwr_enabled_f()); |
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c index 005507bc..212fae62 100644 --- a/drivers/gpu/nvgpu/gm206/bios_gm206.c +++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c | |||
@@ -594,7 +594,7 @@ static int gm206_bios_devinit(struct gk20a *g) | |||
594 | 594 | ||
595 | static int gm206_bios_preos(struct gk20a *g) | 595 | static int gm206_bios_preos(struct gk20a *g) |
596 | { | 596 | { |
597 | int retries = GR_IDLE_CHECK_MAX / GR_IDLE_CHECK_DEFAULT; | 597 | int retries = PMU_BOOT_TIMEOUT_MAX / PMU_BOOT_TIMEOUT_DEFAULT; |
598 | int err = 0; | 598 | int err = 0; |
599 | int val; | 599 | int val; |
600 | 600 | ||
@@ -610,7 +610,7 @@ static int gm206_bios_preos(struct gk20a *g) | |||
610 | gk20a_dbg_fn("done"); | 610 | gk20a_dbg_fn("done"); |
611 | break; | 611 | break; |
612 | } | 612 | } |
613 | udelay(GR_IDLE_CHECK_DEFAULT); | 613 | udelay(PMU_BOOT_TIMEOUT_DEFAULT); |
614 | } while (--retries || !tegra_platform_is_silicon()); | 614 | } while (--retries || !tegra_platform_is_silicon()); |
615 | 615 | ||
616 | /* todo check retries */ | 616 | /* todo check retries */ |