diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 61 |
1 files changed, 55 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index e4f658f6..0d8cd398 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -1191,6 +1191,10 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | |||
1191 | dev->mclk_target_mhz = target_mhz; | 1191 | dev->mclk_target_mhz = target_mhz; |
1192 | break; | 1192 | break; |
1193 | 1193 | ||
1194 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1195 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | ||
1196 | break; | ||
1197 | |||
1194 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | 1198 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: |
1195 | dev->gpc2clk_target_mhz = target_mhz; | 1199 | dev->gpc2clk_target_mhz = target_mhz; |
1196 | break; | 1200 | break; |
@@ -1220,6 +1224,10 @@ int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | |||
1220 | *freq_mhz = target->mclk; | 1224 | *freq_mhz = target->mclk; |
1221 | break; | 1225 | break; |
1222 | 1226 | ||
1227 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1228 | *freq_mhz = target->gpc2clk / 2ULL; | ||
1229 | break; | ||
1230 | |||
1223 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | 1231 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: |
1224 | *freq_mhz = target->gpc2clk; | 1232 | *freq_mhz = target->gpc2clk; |
1225 | break; | 1233 | break; |
@@ -1249,6 +1257,10 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1249 | *freq_mhz = actual->mclk; | 1257 | *freq_mhz = actual->mclk; |
1250 | break; | 1258 | break; |
1251 | 1259 | ||
1260 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
1261 | *freq_mhz = actual->gpc2clk / 2ULL; | ||
1262 | break; | ||
1263 | |||
1252 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: | 1264 | case NVGPU_GPU_CLK_DOMAIN_GPC2CLK: |
1253 | *freq_mhz = actual->gpc2clk; | 1265 | *freq_mhz = actual->gpc2clk; |
1254 | break; | 1266 | break; |
@@ -1264,27 +1276,64 @@ int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | |||
1264 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | 1276 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, |
1265 | u32 api_domain, u16 *freq_mhz) | 1277 | u32 api_domain, u16 *freq_mhz) |
1266 | { | 1278 | { |
1267 | 1279 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) | |
1268 | *freq_mhz = g->ops.clk.get_rate(g, api_domain); | 1280 | *freq_mhz = g->ops.clk.get_rate(g, |
1281 | NVGPU_GPU_CLK_DOMAIN_GPC2CLK) / 2; | ||
1282 | else | ||
1283 | *freq_mhz = g->ops.clk.get_rate(g, api_domain); | ||
1269 | return 0; | 1284 | return 0; |
1270 | } | 1285 | } |
1271 | 1286 | ||
1272 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | 1287 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, |
1273 | u16 *min_mhz, u16 *max_mhz) | 1288 | u16 *min_mhz, u16 *max_mhz) |
1274 | { | 1289 | { |
1275 | return g->ops.clk_arb.get_arbiter_clk_range(g, api_domain, | 1290 | int ret; |
1291 | |||
1292 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) { | ||
1293 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1294 | NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | ||
1295 | min_mhz, max_mhz); | ||
1296 | if (!ret) { | ||
1297 | *min_mhz /= 2; | ||
1298 | *max_mhz /= 2; | ||
1299 | } | ||
1300 | } else { | ||
1301 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, api_domain, | ||
1276 | min_mhz, max_mhz); | 1302 | min_mhz, max_mhz); |
1303 | } | ||
1304 | |||
1305 | return ret; | ||
1277 | } | 1306 | } |
1278 | 1307 | ||
1279 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | 1308 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) |
1280 | { | 1309 | { |
1281 | return g->ops.clk_arb.get_arbiter_clk_domains(g); | 1310 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); |
1311 | |||
1312 | if (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) | ||
1313 | clk_domains |= CTRL_CLK_DOMAIN_GPCCLK; | ||
1314 | |||
1315 | return clk_domains; | ||
1282 | } | 1316 | } |
1283 | 1317 | ||
1284 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | 1318 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, |
1285 | u32 api_domain, u32 *max_points, u16 *fpoints) | 1319 | u32 api_domain, u32 *max_points, u16 *fpoints) |
1286 | { | 1320 | { |
1287 | return (int)clk_domain_get_f_points(g, api_domain, max_points, fpoints); | 1321 | int err; |
1322 | u32 i; | ||
1323 | |||
1324 | if (api_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) { | ||
1325 | err = clk_domain_get_f_points(g, NVGPU_GPU_CLK_DOMAIN_GPC2CLK, | ||
1326 | max_points, fpoints); | ||
1327 | if (err || !fpoints) | ||
1328 | return err; | ||
1329 | for (i = 0; i < *max_points; i++) | ||
1330 | fpoints[i] /= 2; | ||
1331 | } else { | ||
1332 | err = clk_domain_get_f_points(g, api_domain, | ||
1333 | max_points, fpoints); | ||
1334 | } | ||
1335 | |||
1336 | return err; | ||
1288 | } | 1337 | } |
1289 | 1338 | ||
1290 | static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, | 1339 | static u8 nvgpu_clk_arb_find_vf_point(struct nvgpu_clk_arb *arb, |