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-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c67
-rw-r--r--drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h8
-rw-r--r--drivers/gpu/nvgpu/common/power_features/cg/cg.c12
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h4
5 files changed, 73 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
index 418f2c12..57b1443b 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
+++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2019, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -43,9 +43,7 @@ static const struct gating_desc gv11b_slcg_ce2[] = {
43 43
44/* slcg chiplet */ 44/* slcg chiplet */
45static const struct gating_desc gv11b_slcg_chiplet[] = { 45static const struct gating_desc gv11b_slcg_chiplet[] = {
46 {.addr = 0x0010c07cU, .prod = 0x00000000U, .disable = 0x00000007U},
47 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U}, 46 {.addr = 0x0010e07cU, .prod = 0x00000000U, .disable = 0x00000007U},
48 {.addr = 0x0010d07cU, .prod = 0x00000000U, .disable = 0x00000007U},
49 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U}, 47 {.addr = 0x0010e17cU, .prod = 0x00000000U, .disable = 0x00000007U},
50}; 48};
51 49
@@ -70,22 +68,15 @@ static const struct gating_desc gv11b_slcg_gr[] = {
70 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU}, 68 {.addr = 0x00405864U, .prod = 0x00000000U, .disable = 0x000001feU},
71 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, 69 {.addr = 0x00405910U, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
72 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU}, 70 {.addr = 0x00408044U, .prod = 0x00000000U, .disable = 0x000007feU},
73 /* fix priv error */
74 /*{.addr = 0x00407004U, .prod = 0x00000000U, .disable = 0x000001feU},*/
75 /*{.addr = 0x00405bf4U, .prod = 0x00000000U, .disable = 0x00000002U},*/
76 {.addr = 0x0041a134U, .prod = 0x00020008U, .disable = 0x0003fffeU}, 71 {.addr = 0x0041a134U, .prod = 0x00020008U, .disable = 0x0003fffeU},
77 {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU}, 72 {.addr = 0x0041a894U, .prod = 0x00000000U, .disable = 0x0000fffeU},
78 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU}, 73 {.addr = 0x00418504U, .prod = 0x00000000U, .disable = 0x0007fffeU},
79 /* fix priv error */
80 /*{.addr = 0x0041860cU, .prod = 0x00000000U, .disable = 0x000001feU},*/
81 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU}, 74 {.addr = 0x0041868cU, .prod = 0x00000000U, .disable = 0x0000001eU},
82 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU}, 75 {.addr = 0x0041871cU, .prod = 0x00000000U, .disable = 0x000003feU},
83 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U}, 76 {.addr = 0x00418388U, .prod = 0x00000000U, .disable = 0x00000001U},
84 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU}, 77 {.addr = 0x0041882cU, .prod = 0x00000000U, .disable = 0x0001fffeU},
85 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU}, 78 {.addr = 0x00418bc0U, .prod = 0x00000000U, .disable = 0x000001feU},
86 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU}, 79 {.addr = 0x00418974U, .prod = 0x00000000U, .disable = 0x0001fffeU},
87 /* fix priv error */
88 /*{.addr = 0x00418c74U, .prod = 0xffffff80U, .disable = 0xfffffffeU},*/
89 {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU}, 80 {.addr = 0x00418cf4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},
90 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, 81 {.addr = 0x00418d74U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
91 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU}, 82 {.addr = 0x00418f10U, .prod = 0xffffffe0U, .disable = 0xfffffffeU},
@@ -95,8 +86,6 @@ static const struct gating_desc gv11b_slcg_gr[] = {
95 {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU}, 86 {.addr = 0x00419d24U, .prod = 0x00000000U, .disable = 0x000000ffU},
96 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU}, 87 {.addr = 0x0041986cU, .prod = 0x00000104U, .disable = 0x00fffffeU},
97 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU}, 88 {.addr = 0x00419c74U, .prod = 0x0000001eU, .disable = 0x0000001eU},
98 /* fix priv error */
99 /*{.addr = 0x00419c84U, .prod = 0x0003fff8U, .disable = 0x0003fffeU},*/
100 {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU}, 89 {.addr = 0x00419c8cU, .prod = 0xffffff84U, .disable = 0xfffffffeU},
101 {.addr = 0x00419c94U, .prod = 0x00080040U, .disable = 0x000ffffeU}, 90 {.addr = 0x00419c94U, .prod = 0x00080040U, .disable = 0x000ffffeU},
102 {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU}, 91 {.addr = 0x00419ca4U, .prod = 0x00003ffeU, .disable = 0x00003ffeU},
@@ -110,8 +99,6 @@ static const struct gating_desc gv11b_slcg_gr[] = {
110 {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU}, 99 {.addr = 0x00419a84U, .prod = 0x0000000cU, .disable = 0x0000000eU},
111 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU}, 100 {.addr = 0x0041be2cU, .prod = 0x04115fc0U, .disable = 0xfffffffeU},
112 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU}, 101 {.addr = 0x0041bfecU, .prod = 0xfffffff0U, .disable = 0xfffffffeU},
113 /* fix priv error */
114 /*{.addr = 0x0041bed4U, .prod = 0xfffffff8U, .disable = 0xfffffffeU},*/
115 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU}, 102 {.addr = 0x00408814U, .prod = 0x00000000U, .disable = 0x0001fffeU},
116 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU}, 103 {.addr = 0x00408a84U, .prod = 0x00000000U, .disable = 0x0001fffeU},
117 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU}, 104 {.addr = 0x004089acU, .prod = 0x00000000U, .disable = 0x0001fffeU},
@@ -130,8 +117,6 @@ static const struct gating_desc gv11b_slcg_perf[] = {
130 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U}, 117 {.addr = 0x00248018U, .prod = 0xffffffffU, .disable = 0x00000000U},
131 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, 118 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
132 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U}, 119 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
133 {.addr = 0x00246018U, .prod = 0xffffffffU, .disable = 0x00000000U},
134 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
135 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, 120 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
136 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U}, 121 {.addr = 0x00244018U, .prod = 0xffffffffU, .disable = 0x00000000U},
137 {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U}, 122 {.addr = 0x0024a124U, .prod = 0x00000001U, .disable = 0x00000000U},
@@ -168,7 +153,13 @@ static const struct gating_desc gv11b_slcg_xbar[] = {
168 {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU}, 153 {.addr = 0x0013dc08U, .prod = 0x00000000U, .disable = 0xfffffffeU},
169 {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU}, 154 {.addr = 0x0013c924U, .prod = 0x00000000U, .disable = 0x7ffffffeU},
170 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, 155 {.addr = 0x0013cbe4U, .prod = 0x00000000U, .disable = 0x1ffffffeU},
171 {.addr = 0x0013cc04U, .prod = 0x00000000U, .disable = 0x1ffffffeU}, 156};
157
158/* slcg Hshub */
159static const struct gating_desc gv11b_slcg_hshub[] = {
160 {.addr = 0x001fb3f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
161 {.addr = 0x001fb7f4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
162 {.addr = 0x001fbbf4U, .prod = 0x00000000U, .disable = 0xfffffffeU},
172}; 163};
173 164
174/* blcg bus */ 165/* blcg bus */
@@ -191,8 +182,6 @@ static const struct gating_desc gv11b_blcg_fb[] = {
191 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U}, 182 {.addr = 0x00100d30U, .prod = 0x0000c242U, .disable = 0x00000000U},
192 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U}, 183 {.addr = 0x00100d3cU, .prod = 0x00000242U, .disable = 0x00000000U},
193 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U}, 184 {.addr = 0x00100d48U, .prod = 0x0000c242U, .disable = 0x00000000U},
194 /* fix priv error */
195 /*{.addr = 0x00100d1cU, .prod = 0x00000042U, .disable = 0x00000000U},*/
196 {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U}, 185 {.addr = 0x00100c98U, .prod = 0x00004242U, .disable = 0x00000000U},
197}; 186};
198 187
@@ -279,7 +268,13 @@ static const struct gating_desc gv11b_blcg_xbar[] = {
279 {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U}, 268 {.addr = 0x0013dc04U, .prod = 0x0001004aU, .disable = 0x00000000U},
280 {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U}, 269 {.addr = 0x0013c920U, .prod = 0x0000004aU, .disable = 0x00000000U},
281 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U}, 270 {.addr = 0x0013cbe0U, .prod = 0x00000042U, .disable = 0x00000000U},
282 {.addr = 0x0013cc00U, .prod = 0x00000042U, .disable = 0x00000000U}, 271};
272
273/* blcg Hshub */
274static const struct gating_desc gv11b_blcg_hshub[] = {
275 {.addr = 0x001fb3f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
276 {.addr = 0x001fb7f0U, .prod = 0x0000c242U, .disable = 0x00000000U},
277 {.addr = 0x001fbbf0U, .prod = 0x0000c242U, .disable = 0x00000000U},
283}; 278};
284 279
285/* pg gr */ 280/* pg gr */
@@ -502,6 +497,22 @@ void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g,
502 } 497 }
503} 498}
504 499
500void gv11b_slcg_hshub_load_gating_prod(struct gk20a *g,
501 bool prod)
502{
503 u32 i;
504 u32 size = (u32)(sizeof(gv11b_slcg_hshub) / GATING_DESC_SIZE);
505
506 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_SLCG)) {
507 for (i = 0; i < size; i++) {
508 u32 reg = gv11b_slcg_hshub[i].addr;
509 u32 val = prod ? gv11b_slcg_hshub[i].prod :
510 gv11b_slcg_hshub[i].disable;
511 gk20a_writel(g, reg, val);
512 }
513 }
514}
515
505void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, 516void gv11b_blcg_bus_load_gating_prod(struct gk20a *g,
506 bool prod) 517 bool prod)
507{ 518{
@@ -662,6 +673,22 @@ void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g,
662 } 673 }
663} 674}
664 675
676void gv11b_blcg_hshub_load_gating_prod(struct gk20a *g,
677 bool prod)
678{
679 u32 i;
680 u32 size = (u32)(sizeof(gv11b_blcg_hshub) / GATING_DESC_SIZE);
681
682 if (nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
683 for (i = 0; i < size; i++) {
684 u32 reg = gv11b_blcg_hshub[i].addr;
685 u32 val = prod ? gv11b_blcg_hshub[i].prod :
686 gv11b_blcg_hshub[i].disable;
687 gk20a_writel(g, reg, val);
688 }
689 }
690}
691
665void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, 692void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g,
666 bool prod) 693 bool prod)
667{ 694{
diff --git a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h
index 155b6e2e..e1229dcf 100644
--- a/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h
+++ b/drivers/gpu/nvgpu/common/clock_gating/gv11b_gating_reglist.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2016-2018, NVIDIA Corporation. All rights reserved. 2 * Copyright (c) 2016-2019, NVIDIA Corporation. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -69,6 +69,9 @@ void gv11b_slcg_therm_load_gating_prod(struct gk20a *g,
69void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g, 69void gv11b_slcg_xbar_load_gating_prod(struct gk20a *g,
70 bool prod); 70 bool prod);
71 71
72void gv11b_slcg_hshub_load_gating_prod(struct gk20a *g,
73 bool prod);
74
72void gv11b_blcg_bus_load_gating_prod(struct gk20a *g, 75void gv11b_blcg_bus_load_gating_prod(struct gk20a *g,
73 bool prod); 76 bool prod);
74 77
@@ -99,6 +102,9 @@ void gv11b_blcg_pmu_load_gating_prod(struct gk20a *g,
99void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g, 102void gv11b_blcg_xbar_load_gating_prod(struct gk20a *g,
100 bool prod); 103 bool prod);
101 104
105void gv11b_blcg_hshub_load_gating_prod(struct gk20a *g,
106 bool prod);
107
102void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g, 108void gr_gv11b_pg_gr_load_gating_prod(struct gk20a *g,
103 bool prod); 109 bool prod);
104#endif /* GV11B_GATING_REGLIST_H */ 110#endif /* GV11B_GATING_REGLIST_H */
diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
index a538c44b..39796bc8 100644
--- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c
+++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c
@@ -428,6 +428,9 @@ void nvgpu_cg_init_gr_load_gating_prod(struct gk20a *g)
428 if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) { 428 if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
429 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, true); 429 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, true);
430 } 430 }
431 if (g->ops.clock_gating.slcg_hshub_load_gating_prod != NULL) {
432 g->ops.clock_gating.slcg_hshub_load_gating_prod(g, true);
433 }
431 434
432check_can_blcg: 435check_can_blcg:
433 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { 436 if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) {
@@ -449,6 +452,9 @@ check_can_blcg:
449 if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) { 452 if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
450 g->ops.clock_gating.blcg_xbar_load_gating_prod(g, true); 453 g->ops.clock_gating.blcg_xbar_load_gating_prod(g, true);
451 } 454 }
455 if (g->ops.clock_gating.blcg_hshub_load_gating_prod != NULL) {
456 g->ops.clock_gating.blcg_hshub_load_gating_prod(g, true);
457 }
452pg_gr_load: 458pg_gr_load:
453 if (g->ops.clock_gating.pg_gr_load_gating_prod != NULL) { 459 if (g->ops.clock_gating.pg_gr_load_gating_prod != NULL) {
454 g->ops.clock_gating.pg_gr_load_gating_prod(g, true); 460 g->ops.clock_gating.pg_gr_load_gating_prod(g, true);
@@ -538,6 +544,9 @@ void nvgpu_cg_blcg_set_blcg_enabled(struct gk20a *g, bool enable)
538 if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) { 544 if (g->ops.clock_gating.blcg_xbar_load_gating_prod != NULL) {
539 g->ops.clock_gating.blcg_xbar_load_gating_prod(g, enable); 545 g->ops.clock_gating.blcg_xbar_load_gating_prod(g, enable);
540 } 546 }
547 if (g->ops.clock_gating.blcg_hshub_load_gating_prod != NULL) {
548 g->ops.clock_gating.blcg_hshub_load_gating_prod(g, enable);
549 }
541 550
542done: 551done:
543 nvgpu_mutex_release(&g->cg_pg_lock); 552 nvgpu_mutex_release(&g->cg_pg_lock);
@@ -610,6 +619,9 @@ void nvgpu_cg_slcg_set_slcg_enabled(struct gk20a *g, bool enable)
610 if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) { 619 if (g->ops.clock_gating.slcg_xbar_load_gating_prod != NULL) {
611 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, enable); 620 g->ops.clock_gating.slcg_xbar_load_gating_prod(g, enable);
612 } 621 }
622 if (g->ops.clock_gating.slcg_hshub_load_gating_prod != NULL) {
623 g->ops.clock_gating.slcg_hshub_load_gating_prod(g, enable);
624 }
613 625
614done: 626done:
615 nvgpu_mutex_release(&g->cg_pg_lock); 627 nvgpu_mutex_release(&g->cg_pg_lock);
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 84469fa0..38f21bff 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -527,6 +527,8 @@ static const struct gpu_ops gv11b_ops = {
527 gv11b_slcg_therm_load_gating_prod, 527 gv11b_slcg_therm_load_gating_prod,
528 .slcg_xbar_load_gating_prod = 528 .slcg_xbar_load_gating_prod =
529 gv11b_slcg_xbar_load_gating_prod, 529 gv11b_slcg_xbar_load_gating_prod,
530 .slcg_hshub_load_gating_prod =
531 gv11b_slcg_hshub_load_gating_prod,
530 .blcg_bus_load_gating_prod = 532 .blcg_bus_load_gating_prod =
531 gv11b_blcg_bus_load_gating_prod, 533 gv11b_blcg_bus_load_gating_prod,
532 .blcg_ce_load_gating_prod = 534 .blcg_ce_load_gating_prod =
@@ -547,6 +549,8 @@ static const struct gpu_ops gv11b_ops = {
547 gv11b_blcg_pmu_load_gating_prod, 549 gv11b_blcg_pmu_load_gating_prod,
548 .blcg_xbar_load_gating_prod = 550 .blcg_xbar_load_gating_prod =
549 gv11b_blcg_xbar_load_gating_prod, 551 gv11b_blcg_xbar_load_gating_prod,
552 .blcg_hshub_load_gating_prod =
553 gv11b_blcg_hshub_load_gating_prod,
550 .pg_gr_load_gating_prod = 554 .pg_gr_load_gating_prod =
551 gr_gv11b_pg_gr_load_gating_prod, 555 gr_gv11b_pg_gr_load_gating_prod,
552 }, 556 },
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 47a04f16..af8a868e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * GK20A Graphics 4 * GK20A Graphics
5 * 5 *
@@ -616,6 +616,7 @@ struct gpu_ops {
616 void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); 616 void (*slcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
617 void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod); 617 void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod);
618 void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); 618 void (*slcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
619 void (*slcg_hshub_load_gating_prod)(struct gk20a *g, bool prod);
619 void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod); 620 void (*blcg_bus_load_gating_prod)(struct gk20a *g, bool prod);
620 void (*blcg_ce_load_gating_prod)(struct gk20a *g, bool prod); 621 void (*blcg_ce_load_gating_prod)(struct gk20a *g, bool prod);
621 void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod); 622 void (*blcg_ctxsw_firmware_load_gating_prod)(struct gk20a *g, bool prod);
@@ -626,6 +627,7 @@ struct gpu_ops {
626 void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod); 627 void (*blcg_pwr_csb_load_gating_prod)(struct gk20a *g, bool prod);
627 void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod); 628 void (*blcg_pmu_load_gating_prod)(struct gk20a *g, bool prod);
628 void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod); 629 void (*blcg_xbar_load_gating_prod)(struct gk20a *g, bool prod);
630 void (*blcg_hshub_load_gating_prod)(struct gk20a *g, bool prod);
629 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod); 631 void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
630 } clock_gating; 632 } clock_gating;
631 struct { 633 struct {