diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 33 |
1 files changed, 17 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 6ee7dff9..fbdf9368 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1065,7 +1065,7 @@ struct clk *gm20b_clk_get(struct gk20a *g) | |||
1065 | static int gm20b_init_clk_setup_sw(struct gk20a *g) | 1065 | static int gm20b_init_clk_setup_sw(struct gk20a *g) |
1066 | { | 1066 | { |
1067 | struct clk_gk20a *clk = &g->clk; | 1067 | struct clk_gk20a *clk = &g->clk; |
1068 | static int initialized; | 1068 | unsigned long safe_rate; |
1069 | struct clk *ref; | 1069 | struct clk *ref; |
1070 | bool calibrated; | 1070 | bool calibrated; |
1071 | 1071 | ||
@@ -1103,30 +1103,28 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1103 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1103 | clk->gpc_pll.id = GK20A_GPC_PLL; |
1104 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; | 1104 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; |
1105 | 1105 | ||
1106 | safe_rate = tegra_dvfs_get_therm_safe_fmax( | ||
1107 | clk_get_parent(clk->tegra_clk)); | ||
1108 | safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100; | ||
1109 | dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate); | ||
1110 | clk->gpc_pll.PL = DIV_ROUND_UP(gpc_pll_params.min_vco, | ||
1111 | dvfs_safe_max_freq); | ||
1112 | |||
1106 | /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */ | 1113 | /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */ |
1107 | if (!initialized) { | 1114 | clk->gpc_pll.M = 1; |
1108 | initialized = 1; | 1115 | clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco, |
1109 | clk->gpc_pll.M = 1; | 1116 | clk->gpc_pll.clk_in); |
1110 | clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco, | 1117 | clk->gpc_pll.PL = max(clk->gpc_pll.PL, 3U); |
1111 | clk->gpc_pll.clk_in); | 1118 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; |
1112 | clk->gpc_pll.PL = 3; | 1119 | clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL); |
1113 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; | ||
1114 | clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL); | ||
1115 | } | ||
1116 | 1120 | ||
1117 | calibrated = !clk_config_calibration_params(g); | 1121 | calibrated = !clk_config_calibration_params(g); |
1118 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 1122 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
1119 | if (ALLOW_NON_CALIBRATED_NA_MODE || calibrated) { | 1123 | if (ALLOW_NON_CALIBRATED_NA_MODE || calibrated) { |
1120 | /* NA mode is supported only at max update rate 38.4 MHz */ | 1124 | /* NA mode is supported only at max update rate 38.4 MHz */ |
1121 | if (clk->gpc_pll.clk_in == gpc_pll_params.max_u) { | 1125 | if (clk->gpc_pll.clk_in == gpc_pll_params.max_u) { |
1122 | unsigned long safe_rate; | ||
1123 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; | 1126 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; |
1124 | gpc_pll_params.min_u = gpc_pll_params.max_u; | 1127 | gpc_pll_params.min_u = gpc_pll_params.max_u; |
1125 | |||
1126 | safe_rate = tegra_dvfs_get_therm_safe_fmax( | ||
1127 | clk_get_parent(clk->tegra_clk)); | ||
1128 | safe_rate = safe_rate * (100 - DVFS_SAFE_MARGIN) / 100; | ||
1129 | dvfs_safe_max_freq = rate_gpu_to_gpc2clk(safe_rate); | ||
1130 | } | 1128 | } |
1131 | } | 1129 | } |
1132 | #endif | 1130 | #endif |
@@ -1136,6 +1134,9 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1136 | clk->sw_ready = true; | 1134 | clk->sw_ready = true; |
1137 | 1135 | ||
1138 | gk20a_dbg_fn("done"); | 1136 | gk20a_dbg_fn("done"); |
1137 | pr_info("GM20b GPCPLL initial settings:%s M=%u, N=%u, P=%u\n", | ||
1138 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", | ||
1139 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); | ||
1139 | return 0; | 1140 | return 0; |
1140 | } | 1141 | } |
1141 | 1142 | ||