diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 |
2 files changed, 9 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 4da2ef59..3a3406f9 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -2214,8 +2214,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2214 | 2214 | ||
2215 | 2215 | ||
2216 | 2216 | ||
2217 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, | 2217 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c) |
2218 | struct channel_gk20a *c, bool patch) | ||
2219 | { | 2218 | { |
2220 | struct channel_ctx_gk20a *ch_ctx = NULL; | 2219 | struct channel_ctx_gk20a *ch_ctx = NULL; |
2221 | u32 pd_ab_dist_cfg0; | 2220 | u32 pd_ab_dist_cfg0; |
@@ -2230,15 +2229,6 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g, | |||
2230 | ds_debug = gk20a_readl(g, gr_ds_debug_r()); | 2229 | ds_debug = gk20a_readl(g, gr_ds_debug_r()); |
2231 | mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); | 2230 | mpc_vtg_debug = gk20a_readl(g, gr_gpcs_tpcs_mpc_vtg_debug_r()); |
2232 | 2231 | ||
2233 | if (patch) { | ||
2234 | int err; | ||
2235 | |||
2236 | ch_ctx = &c->ch_ctx; | ||
2237 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | ||
2238 | if (err) | ||
2239 | return err; | ||
2240 | } | ||
2241 | |||
2242 | pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); | 2232 | pe_vaf = gk20a_readl(g, gr_gpcs_tpcs_pe_vaf_r()); |
2243 | pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); | 2233 | pe_vsc_vpc = gk20a_readl(g, gr_gpcs_tpcs_pes_vsc_vpc_r()); |
2244 | 2234 | ||
@@ -2252,17 +2242,14 @@ int gr_gv11b_commit_global_timeslice(struct gk20a *g, | |||
2252 | mpc_vtg_debug; | 2242 | mpc_vtg_debug; |
2253 | 2243 | ||
2254 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, | 2244 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pe_vaf_r(), pe_vaf, |
2255 | patch); | 2245 | false); |
2256 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), | 2246 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_pes_vsc_vpc_r(), |
2257 | pe_vsc_vpc, patch); | 2247 | pe_vsc_vpc, false); |
2258 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), | 2248 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_pd_ab_dist_cfg0_r(), |
2259 | pd_ab_dist_cfg0, patch); | 2249 | pd_ab_dist_cfg0, false); |
2260 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, patch); | 2250 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_ds_debug_r(), ds_debug, false); |
2261 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), | 2251 | gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_debug_r(), |
2262 | mpc_vtg_debug, patch); | 2252 | mpc_vtg_debug, false); |
2263 | |||
2264 | if (patch) | ||
2265 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | ||
2266 | 2253 | ||
2267 | return 0; | 2254 | return 0; |
2268 | } | 2255 | } |
@@ -2568,7 +2555,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
2568 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | 2555 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, |
2569 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); | 2556 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); |
2570 | } else { | 2557 | } else { |
2571 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx); | 2558 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); |
2572 | if (err) | 2559 | if (err) |
2573 | goto enable_ctxsw; | 2560 | goto enable_ctxsw; |
2574 | 2561 | ||
@@ -2583,7 +2570,7 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
2583 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask, | 2570 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask, |
2584 | true); | 2571 | true); |
2585 | 2572 | ||
2586 | gr_gk20a_ctx_patch_write_end(g, ch_ctx); | 2573 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); |
2587 | } | 2574 | } |
2588 | 2575 | ||
2589 | enable_ctxsw: | 2576 | enable_ctxsw: |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 98e7bc50..b6ba231e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -142,8 +142,7 @@ void gr_gv11b_program_sm_id_numbering(struct gk20a *g, | |||
142 | u32 gpc, u32 tpc, u32 smid); | 142 | u32 gpc, u32 tpc, u32 smid); |
143 | int gr_gv11b_load_smid_config(struct gk20a *g); | 143 | int gr_gv11b_load_smid_config(struct gk20a *g); |
144 | int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); | 144 | int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va); |
145 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, | 145 | int gr_gv11b_commit_global_timeslice(struct gk20a *g, struct channel_gk20a *c); |
146 | struct channel_gk20a *c, bool patch); | ||
147 | void gr_gv11b_write_zcull_ptr(struct gk20a *g, | 146 | void gr_gv11b_write_zcull_ptr(struct gk20a *g, |
148 | struct nvgpu_mem *mem, u64 gpu_va); | 147 | struct nvgpu_mem *mem, u64 gpu_va); |
149 | void gr_gv11b_write_pm_ptr(struct gk20a *g, | 148 | void gr_gv11b_write_pm_ptr(struct gk20a *g, |