diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 324 |
1 files changed, 212 insertions, 112 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index ee736d15..1e001824 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -210,8 +210,9 @@ static int gr_gv11b_handle_l1_tag_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
210 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m() | | 210 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_pixrpf_m() | |
211 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()); | 211 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_uncorrected_err_miss_fifo_m()); |
212 | 212 | ||
213 | if ((l1_tag_ecc_corrected_err_status == 0) && (l1_tag_ecc_uncorrected_err_status == 0)) | 213 | if ((l1_tag_ecc_corrected_err_status == 0) && (l1_tag_ecc_uncorrected_err_status == 0)) { |
214 | return 0; | 214 | return 0; |
215 | } | ||
215 | 216 | ||
216 | l1_tag_corrected_err_count_delta = | 217 | l1_tag_corrected_err_count_delta = |
217 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v( | 218 | gr_pri_gpc0_tpc0_sm_l1_tag_ecc_corrected_err_count_total_v( |
@@ -302,8 +303,9 @@ static int gr_gv11b_handle_lrf_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
302 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m() | | 303 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp6_m() | |
303 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()); | 304 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_uncorrected_err_qrfdp7_m()); |
304 | 305 | ||
305 | if ((lrf_ecc_corrected_err_status == 0) && (lrf_ecc_uncorrected_err_status == 0)) | 306 | if ((lrf_ecc_corrected_err_status == 0) && (lrf_ecc_uncorrected_err_status == 0)) { |
306 | return 0; | 307 | return 0; |
308 | } | ||
307 | 309 | ||
308 | lrf_corrected_err_count_delta = | 310 | lrf_corrected_err_count_delta = |
309 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v( | 311 | gr_pri_gpc0_tpc0_sm_lrf_ecc_corrected_err_count_total_v( |
@@ -461,8 +463,9 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
461 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m() | | 463 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm0_m() | |
462 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()); | 464 | gr_pri_gpc0_tpc0_sm_cbu_ecc_status_uncorrected_err_barrier_sm1_m()); |
463 | 465 | ||
464 | if ((cbu_ecc_corrected_err_status == 0) && (cbu_ecc_uncorrected_err_status == 0)) | 466 | if ((cbu_ecc_corrected_err_status == 0) && (cbu_ecc_uncorrected_err_status == 0)) { |
465 | return 0; | 467 | return 0; |
468 | } | ||
466 | 469 | ||
467 | cbu_corrected_err_count_delta = | 470 | cbu_corrected_err_count_delta = |
468 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v( | 471 | gr_pri_gpc0_tpc0_sm_cbu_ecc_corrected_err_count_total_v( |
@@ -541,8 +544,9 @@ static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
541 | (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m() | | 544 | (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m() | |
542 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()); | 545 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()); |
543 | 546 | ||
544 | if ((l1_data_ecc_corrected_err_status == 0) && (l1_data_ecc_uncorrected_err_status == 0)) | 547 | if ((l1_data_ecc_corrected_err_status == 0) && (l1_data_ecc_uncorrected_err_status == 0)) { |
545 | return 0; | 548 | return 0; |
549 | } | ||
546 | 550 | ||
547 | l1_data_corrected_err_count_delta = | 551 | l1_data_corrected_err_count_delta = |
548 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v( | 552 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v( |
@@ -625,8 +629,9 @@ static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
625 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m() | | 629 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m() | |
626 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()); | 630 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()); |
627 | 631 | ||
628 | if ((icache_ecc_corrected_err_status == 0) && (icache_ecc_uncorrected_err_status == 0)) | 632 | if ((icache_ecc_corrected_err_status == 0) && (icache_ecc_uncorrected_err_status == 0)) { |
629 | return 0; | 633 | return 0; |
634 | } | ||
630 | 635 | ||
631 | icache_corrected_err_count_delta = | 636 | icache_corrected_err_count_delta = |
632 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v( | 637 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v( |
@@ -729,8 +734,9 @@ int gr_gv11b_handle_gcc_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
729 | (gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m() | | 734 | (gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank0_m() | |
730 | gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()); | 735 | gr_pri_gpc0_gcc_l15_ecc_status_uncorrected_err_bank1_m()); |
731 | 736 | ||
732 | if ((gcc_l15_ecc_corrected_err_status == 0) && (gcc_l15_ecc_uncorrected_err_status == 0)) | 737 | if ((gcc_l15_ecc_corrected_err_status == 0) && (gcc_l15_ecc_uncorrected_err_status == 0)) { |
733 | return 0; | 738 | return 0; |
739 | } | ||
734 | 740 | ||
735 | gcc_l15_corrected_err_count_delta = | 741 | gcc_l15_corrected_err_count_delta = |
736 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v( | 742 | gr_pri_gpc0_gcc_l15_ecc_corrected_err_count_total_v( |
@@ -798,8 +804,9 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, | |||
798 | hww_esr = gk20a_readl(g, gr_gpc0_mmu_gpcmmu_global_esr_r() + offset); | 804 | hww_esr = gk20a_readl(g, gr_gpc0_mmu_gpcmmu_global_esr_r() + offset); |
799 | 805 | ||
800 | if (!(hww_esr & (gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m() | | 806 | if (!(hww_esr & (gr_gpc0_mmu_gpcmmu_global_esr_ecc_corrected_m() | |
801 | gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m()))) | 807 | gr_gpc0_mmu_gpcmmu_global_esr_ecc_uncorrected_m()))) { |
802 | return ret; | 808 | return ret; |
809 | } | ||
803 | 810 | ||
804 | ecc_status = gk20a_readl(g, | 811 | ecc_status = gk20a_readl(g, |
805 | gr_gpc0_mmu_l1tlb_ecc_status_r() + offset); | 812 | gr_gpc0_mmu_l1tlb_ecc_status_r() + offset); |
@@ -822,23 +829,27 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, | |||
822 | 829 | ||
823 | 830 | ||
824 | /* clear the interrupt */ | 831 | /* clear the interrupt */ |
825 | if ((corrected_delta > 0) || corrected_overflow) | 832 | if ((corrected_delta > 0) || corrected_overflow) { |
826 | gk20a_writel(g, | 833 | gk20a_writel(g, |
827 | gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r() + | 834 | gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_r() + |
828 | offset, 0); | 835 | offset, 0); |
829 | if ((uncorrected_delta > 0) || uncorrected_overflow) | 836 | } |
837 | if ((uncorrected_delta > 0) || uncorrected_overflow) { | ||
830 | gk20a_writel(g, | 838 | gk20a_writel(g, |
831 | gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r() + | 839 | gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_r() + |
832 | offset, 0); | 840 | offset, 0); |
841 | } | ||
833 | 842 | ||
834 | gk20a_writel(g, gr_gpc0_mmu_l1tlb_ecc_status_r() + offset, | 843 | gk20a_writel(g, gr_gpc0_mmu_l1tlb_ecc_status_r() + offset, |
835 | gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f()); | 844 | gr_gpc0_mmu_l1tlb_ecc_status_reset_task_f()); |
836 | 845 | ||
837 | /* Handle overflow */ | 846 | /* Handle overflow */ |
838 | if (corrected_overflow) | 847 | if (corrected_overflow) { |
839 | corrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s()); | 848 | corrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_corrected_err_count_total_s()); |
840 | if (uncorrected_overflow) | 849 | } |
850 | if (uncorrected_overflow) { | ||
841 | uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); | 851 | uncorrected_delta += (0x1UL << gr_gpc0_mmu_l1tlb_ecc_uncorrected_err_count_total_s()); |
852 | } | ||
842 | 853 | ||
843 | 854 | ||
844 | g->ecc.gr.mmu_l1tlb_ecc_corrected_err_count[gpc].counter += | 855 | g->ecc.gr.mmu_l1tlb_ecc_corrected_err_count[gpc].counter += |
@@ -848,16 +859,21 @@ static int gr_gv11b_handle_gpcmmu_ecc_exception(struct gk20a *g, u32 gpc, | |||
848 | nvgpu_log(g, gpu_dbg_intr, | 859 | nvgpu_log(g, gpu_dbg_intr, |
849 | "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); | 860 | "mmu l1tlb gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); |
850 | 861 | ||
851 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()) | 862 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_sa_data_m()) { |
852 | nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error"); | 863 | nvgpu_log(g, gpu_dbg_intr, "corrected ecc sa data error"); |
853 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()) | 864 | } |
865 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_sa_data_m()) { | ||
854 | nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error"); | 866 | nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc sa data error"); |
855 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()) | 867 | } |
868 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_corrected_err_l1tlb_fa_data_m()) { | ||
856 | nvgpu_log(g, gpu_dbg_intr, "corrected ecc fa data error"); | 869 | nvgpu_log(g, gpu_dbg_intr, "corrected ecc fa data error"); |
857 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()) | 870 | } |
871 | if (ecc_status & gr_gpc0_mmu_l1tlb_ecc_status_uncorrected_err_l1tlb_fa_data_m()) { | ||
858 | nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc fa data error"); | 872 | nvgpu_log(g, gpu_dbg_intr, "uncorrected ecc fa data error"); |
859 | if (corrected_overflow || uncorrected_overflow) | 873 | } |
874 | if (corrected_overflow || uncorrected_overflow) { | ||
860 | nvgpu_info(g, "mmu l1tlb ecc counter overflow!"); | 875 | nvgpu_info(g, "mmu l1tlb ecc counter overflow!"); |
876 | } | ||
861 | 877 | ||
862 | nvgpu_log(g, gpu_dbg_intr, | 878 | nvgpu_log(g, gpu_dbg_intr, |
863 | "ecc error address: 0x%x", ecc_addr); | 879 | "ecc error address: 0x%x", ecc_addr); |
@@ -883,8 +899,9 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
883 | hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); | 899 | hww_esr = gk20a_readl(g, gr_gpc0_gpccs_hww_esr_r() + offset); |
884 | 900 | ||
885 | if (!(hww_esr & (gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() | | 901 | if (!(hww_esr & (gr_gpc0_gpccs_hww_esr_ecc_uncorrected_m() | |
886 | gr_gpc0_gpccs_hww_esr_ecc_corrected_m()))) | 902 | gr_gpc0_gpccs_hww_esr_ecc_corrected_m()))) { |
887 | return ret; | 903 | return ret; |
904 | } | ||
888 | 905 | ||
889 | ecc_status = gk20a_readl(g, | 906 | ecc_status = gk20a_readl(g, |
890 | gr_gpc0_gpccs_falcon_ecc_status_r() + offset); | 907 | gr_gpc0_gpccs_falcon_ecc_status_r() + offset); |
@@ -907,14 +924,16 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
907 | 924 | ||
908 | 925 | ||
909 | /* clear the interrupt */ | 926 | /* clear the interrupt */ |
910 | if ((corrected_delta > 0) || corrected_overflow) | 927 | if ((corrected_delta > 0) || corrected_overflow) { |
911 | gk20a_writel(g, | 928 | gk20a_writel(g, |
912 | gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + | 929 | gr_gpc0_gpccs_falcon_ecc_corrected_err_count_r() + |
913 | offset, 0); | 930 | offset, 0); |
914 | if ((uncorrected_delta > 0) || uncorrected_overflow) | 931 | } |
932 | if ((uncorrected_delta > 0) || uncorrected_overflow) { | ||
915 | gk20a_writel(g, | 933 | gk20a_writel(g, |
916 | gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + | 934 | gr_gpc0_gpccs_falcon_ecc_uncorrected_err_count_r() + |
917 | offset, 0); | 935 | offset, 0); |
936 | } | ||
918 | 937 | ||
919 | gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, | 938 | gk20a_writel(g, gr_gpc0_gpccs_falcon_ecc_status_r() + offset, |
920 | gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); | 939 | gr_gpc0_gpccs_falcon_ecc_status_reset_task_f()); |
@@ -926,19 +945,24 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
926 | nvgpu_log(g, gpu_dbg_intr, | 945 | nvgpu_log(g, gpu_dbg_intr, |
927 | "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); | 946 | "gppcs gpc:%d ecc interrupt intr: 0x%x", gpc, hww_esr); |
928 | 947 | ||
929 | if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) | 948 | if (ecc_status & gr_gpc0_gpccs_falcon_ecc_status_corrected_err_imem_m()) { |
930 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); | 949 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); |
950 | } | ||
931 | if (ecc_status & | 951 | if (ecc_status & |
932 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) | 952 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_imem_m()) { |
933 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected"); | 953 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error uncorrected"); |
954 | } | ||
934 | if (ecc_status & | 955 | if (ecc_status & |
935 | gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) | 956 | gr_gpc0_gpccs_falcon_ecc_status_corrected_err_dmem_m()) { |
936 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); | 957 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); |
958 | } | ||
937 | if (ecc_status & | 959 | if (ecc_status & |
938 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) | 960 | gr_gpc0_gpccs_falcon_ecc_status_uncorrected_err_dmem_m()) { |
939 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); | 961 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error uncorrected"); |
940 | if (corrected_overflow || uncorrected_overflow) | 962 | } |
963 | if (corrected_overflow || uncorrected_overflow) { | ||
941 | nvgpu_info(g, "gpccs ecc counter overflow!"); | 964 | nvgpu_info(g, "gpccs ecc counter overflow!"); |
965 | } | ||
942 | 966 | ||
943 | nvgpu_log(g, gpu_dbg_intr, | 967 | nvgpu_log(g, gpu_dbg_intr, |
944 | "ecc error row address: 0x%x", | 968 | "ecc error row address: 0x%x", |
@@ -955,18 +979,20 @@ static int gr_gv11b_handle_gpccs_ecc_exception(struct gk20a *g, u32 gpc, | |||
955 | int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, | 979 | int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, |
956 | u32 gpc_exception) | 980 | u32 gpc_exception) |
957 | { | 981 | { |
958 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) | 982 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpcmmu_m()) { |
959 | return gr_gv11b_handle_gpcmmu_ecc_exception(g, gpc, | 983 | return gr_gv11b_handle_gpcmmu_ecc_exception(g, gpc, |
960 | gpc_exception); | 984 | gpc_exception); |
985 | } | ||
961 | return 0; | 986 | return 0; |
962 | } | 987 | } |
963 | 988 | ||
964 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | 989 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, |
965 | u32 gpc_exception) | 990 | u32 gpc_exception) |
966 | { | 991 | { |
967 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) | 992 | if (gpc_exception & gr_gpc0_gpccs_gpc_exception_gpccs_m()) { |
968 | return gr_gv11b_handle_gpccs_ecc_exception(g, gpc, | 993 | return gr_gv11b_handle_gpccs_ecc_exception(g, gpc, |
969 | gpc_exception); | 994 | gpc_exception); |
995 | } | ||
970 | 996 | ||
971 | return 0; | 997 | return 0; |
972 | } | 998 | } |
@@ -1047,8 +1073,9 @@ bool gr_gv11b_add_zbc_type_s(struct gk20a *g, struct gr_gk20a *gr, | |||
1047 | *ret_val = g->ops.gr.add_zbc_s(g, gr, | 1073 | *ret_val = g->ops.gr.add_zbc_s(g, gr, |
1048 | zbc_val, gr->max_used_s_index); | 1074 | zbc_val, gr->max_used_s_index); |
1049 | 1075 | ||
1050 | if (!(*ret_val)) | 1076 | if (!(*ret_val)) { |
1051 | gr->max_used_s_index++; | 1077 | gr->max_used_s_index++; |
1078 | } | ||
1052 | } | 1079 | } |
1053 | return added; | 1080 | return added; |
1054 | } | 1081 | } |
@@ -1122,8 +1149,9 @@ int gr_gv11b_load_stencil_tbl(struct gk20a *g, struct gr_gk20a *gr) | |||
1122 | zbc_val.format = s_tbl->format; | 1149 | zbc_val.format = s_tbl->format; |
1123 | 1150 | ||
1124 | ret = g->ops.gr.add_zbc_s(g, gr, &zbc_val, i); | 1151 | ret = g->ops.gr.add_zbc_s(g, gr, &zbc_val, i); |
1125 | if (ret) | 1152 | if (ret) { |
1126 | return ret; | 1153 | return ret; |
1154 | } | ||
1127 | } | 1155 | } |
1128 | return 0; | 1156 | return 0; |
1129 | } | 1157 | } |
@@ -1248,14 +1276,15 @@ void gr_gv11b_set_shader_cut_collector(struct gk20a *g, u32 data) | |||
1248 | nvgpu_log_fn(g, "gr_gv11b_set_shader_cut_collector"); | 1276 | nvgpu_log_fn(g, "gr_gv11b_set_shader_cut_collector"); |
1249 | 1277 | ||
1250 | val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r()); | 1278 | val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r()); |
1251 | if (data & NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE) | 1279 | if (data & NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE) { |
1252 | val = set_field(val, | 1280 | val = set_field(val, |
1253 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), | 1281 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), |
1254 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f()); | 1282 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f()); |
1255 | else | 1283 | } else { |
1256 | val = set_field(val, | 1284 | val = set_field(val, |
1257 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), | 1285 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), |
1258 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f()); | 1286 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f()); |
1287 | } | ||
1259 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); | 1288 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); |
1260 | } | 1289 | } |
1261 | 1290 | ||
@@ -1339,9 +1368,10 @@ void gr_gv11b_cb_size_default(struct gk20a *g) | |||
1339 | { | 1368 | { |
1340 | struct gr_gk20a *gr = &g->gr; | 1369 | struct gr_gk20a *gr = &g->gr; |
1341 | 1370 | ||
1342 | if (!gr->attrib_cb_default_size) | 1371 | if (!gr->attrib_cb_default_size) { |
1343 | gr->attrib_cb_default_size = | 1372 | gr->attrib_cb_default_size = |
1344 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); | 1373 | gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(); |
1374 | } | ||
1345 | gr->alpha_cb_default_size = | 1375 | gr->alpha_cb_default_size = |
1346 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); | 1376 | gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); |
1347 | gr->attrib_cb_gfxp_default_size = | 1377 | gr->attrib_cb_gfxp_default_size = |
@@ -1359,8 +1389,9 @@ void gr_gv11b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) | |||
1359 | 1389 | ||
1360 | nvgpu_log_fn(g, " "); | 1390 | nvgpu_log_fn(g, " "); |
1361 | 1391 | ||
1362 | if (alpha_cb_size > gr->alpha_cb_size) | 1392 | if (alpha_cb_size > gr->alpha_cb_size) { |
1363 | alpha_cb_size = gr->alpha_cb_size; | 1393 | alpha_cb_size = gr->alpha_cb_size; |
1394 | } | ||
1364 | 1395 | ||
1365 | gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), | 1396 | gk20a_writel(g, gr_ds_tga_constraintlogic_alpha_r(), |
1366 | (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & | 1397 | (gk20a_readl(g, gr_ds_tga_constraintlogic_alpha_r()) & |
@@ -1404,8 +1435,9 @@ void gr_gv11b_set_circular_buffer_size(struct gk20a *g, u32 data) | |||
1404 | 1435 | ||
1405 | nvgpu_log_fn(g, " "); | 1436 | nvgpu_log_fn(g, " "); |
1406 | 1437 | ||
1407 | if (cb_size_steady > gr->attrib_cb_size) | 1438 | if (cb_size_steady > gr->attrib_cb_size) { |
1408 | cb_size_steady = gr->attrib_cb_size; | 1439 | cb_size_steady = gr->attrib_cb_size; |
1440 | } | ||
1409 | if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != | 1441 | if (gk20a_readl(g, gr_gpc0_ppc0_cbm_beta_cb_size_r()) != |
1410 | gk20a_readl(g, | 1442 | gk20a_readl(g, |
1411 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { | 1443 | gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_r())) { |
@@ -1470,8 +1502,9 @@ int gr_gv11b_alloc_buffer(struct vm_gk20a *vm, size_t size, | |||
1470 | nvgpu_log_fn(g, " "); | 1502 | nvgpu_log_fn(g, " "); |
1471 | 1503 | ||
1472 | err = nvgpu_dma_alloc_sys(vm->mm->g, size, mem); | 1504 | err = nvgpu_dma_alloc_sys(vm->mm->g, size, mem); |
1473 | if (err) | 1505 | if (err) { |
1474 | return err; | 1506 | return err; |
1507 | } | ||
1475 | 1508 | ||
1476 | mem->gpu_va = nvgpu_gmmu_map(vm, | 1509 | mem->gpu_va = nvgpu_gmmu_map(vm, |
1477 | mem, | 1510 | mem, |
@@ -1502,29 +1535,35 @@ int gr_gv11b_set_ctxsw_preemption_mode(struct gk20a *g, | |||
1502 | int err = 0; | 1535 | int err = 0; |
1503 | 1536 | ||
1504 | if (g->ops.gr.is_valid_gfx_class(g, class) && | 1537 | if (g->ops.gr.is_valid_gfx_class(g, class) && |
1505 | g->gr.ctx_vars.force_preemption_gfxp) | 1538 | g->gr.ctx_vars.force_preemption_gfxp) { |
1506 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; | 1539 | graphics_preempt_mode = NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP; |
1540 | } | ||
1507 | 1541 | ||
1508 | if (g->ops.gr.is_valid_compute_class(g, class) && | 1542 | if (g->ops.gr.is_valid_compute_class(g, class) && |
1509 | g->gr.ctx_vars.force_preemption_cilp) | 1543 | g->gr.ctx_vars.force_preemption_cilp) { |
1510 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; | 1544 | compute_preempt_mode = NVGPU_PREEMPTION_MODE_COMPUTE_CILP; |
1545 | } | ||
1511 | 1546 | ||
1512 | /* check for invalid combinations */ | 1547 | /* check for invalid combinations */ |
1513 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) | 1548 | if ((graphics_preempt_mode == 0) && (compute_preempt_mode == 0)) { |
1514 | return -EINVAL; | 1549 | return -EINVAL; |
1550 | } | ||
1515 | 1551 | ||
1516 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && | 1552 | if ((graphics_preempt_mode == NVGPU_PREEMPTION_MODE_GRAPHICS_GFXP) && |
1517 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) | 1553 | (compute_preempt_mode == NVGPU_PREEMPTION_MODE_COMPUTE_CILP)) { |
1518 | return -EINVAL; | 1554 | return -EINVAL; |
1555 | } | ||
1519 | 1556 | ||
1520 | /* Do not allow lower preemption modes than current ones */ | 1557 | /* Do not allow lower preemption modes than current ones */ |
1521 | if (graphics_preempt_mode && | 1558 | if (graphics_preempt_mode && |
1522 | (graphics_preempt_mode < gr_ctx->graphics_preempt_mode)) | 1559 | (graphics_preempt_mode < gr_ctx->graphics_preempt_mode)) { |
1523 | return -EINVAL; | 1560 | return -EINVAL; |
1561 | } | ||
1524 | 1562 | ||
1525 | if (compute_preempt_mode && | 1563 | if (compute_preempt_mode && |
1526 | (compute_preempt_mode < gr_ctx->compute_preempt_mode)) | 1564 | (compute_preempt_mode < gr_ctx->compute_preempt_mode)) { |
1527 | return -EINVAL; | 1565 | return -EINVAL; |
1566 | } | ||
1528 | 1567 | ||
1529 | /* set preemption modes */ | 1568 | /* set preemption modes */ |
1530 | switch (graphics_preempt_mode) { | 1569 | switch (graphics_preempt_mode) { |
@@ -1636,8 +1675,9 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1636 | nvgpu_log_fn(g, " "); | 1675 | nvgpu_log_fn(g, " "); |
1637 | 1676 | ||
1638 | tsg = tsg_gk20a_from_ch(c); | 1677 | tsg = tsg_gk20a_from_ch(c); |
1639 | if (!tsg) | 1678 | if (!tsg) { |
1640 | return; | 1679 | return; |
1680 | } | ||
1641 | 1681 | ||
1642 | gr_ctx = &tsg->gr_ctx; | 1682 | gr_ctx = &tsg->gr_ctx; |
1643 | 1683 | ||
@@ -1671,12 +1711,13 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1671 | u32 cbes_reserve; | 1711 | u32 cbes_reserve; |
1672 | 1712 | ||
1673 | if (g->ops.gr.set_preemption_buffer_va) { | 1713 | if (g->ops.gr.set_preemption_buffer_va) { |
1674 | if (ctxheader->gpu_va) | 1714 | if (ctxheader->gpu_va) { |
1675 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, | 1715 | g->ops.gr.set_preemption_buffer_va(g, ctxheader, |
1676 | gr_ctx->preempt_ctxsw_buffer.gpu_va); | 1716 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1677 | else | 1717 | } else { |
1678 | g->ops.gr.set_preemption_buffer_va(g, mem, | 1718 | g->ops.gr.set_preemption_buffer_va(g, mem, |
1679 | gr_ctx->preempt_ctxsw_buffer.gpu_va); | 1719 | gr_ctx->preempt_ctxsw_buffer.gpu_va); |
1720 | } | ||
1680 | } | 1721 | } |
1681 | 1722 | ||
1682 | err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, true); | 1723 | err = gr_gk20a_ctx_patch_write_begin(g, gr_ctx, true); |
@@ -1699,8 +1740,9 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1699 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); | 1740 | (32 - gr_scc_pagepool_base_addr_39_8_align_bits_v())); |
1700 | size = gr_ctx->pagepool_ctxsw_buffer.size; | 1741 | size = gr_ctx->pagepool_ctxsw_buffer.size; |
1701 | 1742 | ||
1702 | if (size == g->ops.gr.pagepool_default_size(g)) | 1743 | if (size == g->ops.gr.pagepool_default_size(g)) { |
1703 | size = gr_scc_pagepool_total_pages_hwmax_v(); | 1744 | size = gr_scc_pagepool_total_pages_hwmax_v(); |
1745 | } | ||
1704 | 1746 | ||
1705 | g->ops.gr.commit_global_pagepool(g, gr_ctx, addr, size, true); | 1747 | g->ops.gr.commit_global_pagepool(g, gr_ctx, addr, size, true); |
1706 | 1748 | ||
@@ -1876,9 +1918,10 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1876 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); | 1918 | gk20a_readl(g, gr_pri_gpc0_gpccs_gpc_activity3_r())); |
1877 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1919 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1878 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); | 1920 | gk20a_readl(g, gr_pri_gpc0_tpc0_tpccs_tpc_activity_0_r())); |
1879 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 1921 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
1880 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1922 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1881 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); | 1923 | gk20a_readl(g, gr_pri_gpc0_tpc1_tpccs_tpc_activity_0_r())); |
1924 | } | ||
1882 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1925 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPC0_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1883 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); | 1926 | gk20a_readl(g, gr_pri_gpc0_tpcs_tpccs_tpc_activity_0_r())); |
1884 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", | 1927 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_GPCCS_GPC_ACTIVITY0: 0x%x\n", |
@@ -1891,9 +1934,10 @@ int gr_gv11b_dump_gr_status_regs(struct gk20a *g, | |||
1891 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); | 1934 | gk20a_readl(g, gr_pri_gpcs_gpccs_gpc_activity_3_r())); |
1892 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1935 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC0_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1893 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); | 1936 | gk20a_readl(g, gr_pri_gpcs_tpc0_tpccs_tpc_activity_0_r())); |
1894 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) | 1937 | if (gr->gpc_tpc_count && gr->gpc_tpc_count[0] == 2) { |
1895 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1938 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPC1_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1896 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); | 1939 | gk20a_readl(g, gr_pri_gpcs_tpc1_tpccs_tpc_activity_0_r())); |
1940 | } | ||
1897 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", | 1941 | gk20a_debug_output(o, "NV_PGRAPH_PRI_GPCS_TPCS_TPCCS_TPC_ACTIVITY0: 0x%x\n", |
1898 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); | 1942 | gk20a_readl(g, gr_pri_gpcs_tpcs_tpccs_tpc_activity_0_r())); |
1899 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", | 1943 | gk20a_debug_output(o, "NV_PGRAPH_PRI_BE0_BECS_BE_ACTIVITY0: 0x%x\n", |
@@ -1973,8 +2017,9 @@ static bool gr_activity_empty_or_preempted(u32 val) | |||
1973 | while (val) { | 2017 | while (val) { |
1974 | u32 v = val & 7; | 2018 | u32 v = val & 7; |
1975 | if (v != gr_activity_4_gpc0_empty_v() && | 2019 | if (v != gr_activity_4_gpc0_empty_v() && |
1976 | v != gr_activity_4_gpc0_preempted_v()) | 2020 | v != gr_activity_4_gpc0_preempted_v()) { |
1977 | return false; | 2021 | return false; |
2022 | } | ||
1978 | val >>= 3; | 2023 | val >>= 3; |
1979 | } | 2024 | } |
1980 | 2025 | ||
@@ -2039,10 +2084,11 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
2039 | { | 2084 | { |
2040 | int attrBufferSize; | 2085 | int attrBufferSize; |
2041 | 2086 | ||
2042 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) | 2087 | if (gr_ctx->preempt_ctxsw_buffer.gpu_va) { |
2043 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; | 2088 | attrBufferSize = gr_ctx->betacb_ctxsw_buffer.size; |
2044 | else | 2089 | } else { |
2045 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); | 2090 | attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g); |
2091 | } | ||
2046 | 2092 | ||
2047 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); | 2093 | attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(); |
2048 | 2094 | ||
@@ -2064,8 +2110,9 @@ void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
2064 | { | 2110 | { |
2065 | u32 fuse_val; | 2111 | u32 fuse_val; |
2066 | 2112 | ||
2067 | if (!g->gr.gpc_tpc_mask[gpc_index]) | 2113 | if (!g->gr.gpc_tpc_mask[gpc_index]) { |
2068 | return; | 2114 | return; |
2115 | } | ||
2069 | 2116 | ||
2070 | /* | 2117 | /* |
2071 | * For s/w value g->gr.gpc_tpc_mask[gpc_index], bit value 1 indicates | 2118 | * For s/w value g->gr.gpc_tpc_mask[gpc_index], bit value 1 indicates |
@@ -2152,8 +2199,9 @@ static int gr_gv11b_handle_warp_esr_error_mmu_nack(struct gk20a *g, | |||
2152 | * recovery path even if channel is invalid. We want to explicitly check | 2199 | * recovery path even if channel is invalid. We want to explicitly check |
2153 | * for teardown value in mmu fault handler. | 2200 | * for teardown value in mmu fault handler. |
2154 | */ | 2201 | */ |
2155 | if (!err) | 2202 | if (!err) { |
2156 | gk20a_channel_put(fault_ch); | 2203 | gk20a_channel_put(fault_ch); |
2204 | } | ||
2157 | 2205 | ||
2158 | /* clear interrupt */ | 2206 | /* clear interrupt */ |
2159 | offset = gk20a_gr_gpc_offset(g, gpc) + | 2207 | offset = gk20a_gr_gpc_offset(g, gpc) + |
@@ -2315,9 +2363,10 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2315 | * We don't need to trigger CILP in case of MMU_NACK | 2363 | * We don't need to trigger CILP in case of MMU_NACK |
2316 | * So just handle MMU_NACK and return | 2364 | * So just handle MMU_NACK and return |
2317 | */ | 2365 | */ |
2318 | if (warp_esr_error == gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f()) | 2366 | if (warp_esr_error == gr_gpc0_tpc0_sm0_hww_warp_esr_error_mmu_nack_f()) { |
2319 | return gr_gv11b_handle_warp_esr_error_mmu_nack(g, gpc, tpc, sm, | 2367 | return gr_gv11b_handle_warp_esr_error_mmu_nack(g, gpc, tpc, sm, |
2320 | warp_esr_error, fault_ch); | 2368 | warp_esr_error, fault_ch); |
2369 | } | ||
2321 | 2370 | ||
2322 | /* | 2371 | /* |
2323 | * Proceed to trigger CILP preemption if the return value | 2372 | * Proceed to trigger CILP preemption if the return value |
@@ -2331,8 +2380,9 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2331 | 2380 | ||
2332 | if (fault_ch) { | 2381 | if (fault_ch) { |
2333 | tsg = tsg_gk20a_from_ch(fault_ch); | 2382 | tsg = tsg_gk20a_from_ch(fault_ch); |
2334 | if (!tsg) | 2383 | if (!tsg) { |
2335 | return -EINVAL; | 2384 | return -EINVAL; |
2385 | } | ||
2336 | 2386 | ||
2337 | cilp_enabled = (tsg->gr_ctx.compute_preempt_mode == | 2387 | cilp_enabled = (tsg->gr_ctx.compute_preempt_mode == |
2338 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); | 2388 | NVGPU_PREEMPTION_MODE_COMPUTE_CILP); |
@@ -2343,13 +2393,15 @@ int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
2343 | gpc, tpc, sm, global_esr); | 2393 | gpc, tpc, sm, global_esr); |
2344 | 2394 | ||
2345 | if (cilp_enabled && sm_debugger_attached) { | 2395 | if (cilp_enabled && sm_debugger_attached) { |
2346 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) | 2396 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()) { |
2347 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | 2397 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, |
2348 | gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()); | 2398 | gr_gpc0_tpc0_sm0_hww_global_esr_bpt_int_pending_f()); |
2399 | } | ||
2349 | 2400 | ||
2350 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()) | 2401 | if (global_esr & gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()) { |
2351 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | 2402 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, |
2352 | gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); | 2403 | gr_gpc0_tpc0_sm0_hww_global_esr_single_step_complete_pending_f()); |
2404 | } | ||
2353 | 2405 | ||
2354 | global_mask = gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() | | 2406 | global_mask = gr_gpc0_tpc0_sm0_hww_global_esr_multiple_warp_errors_pending_f() | |
2355 | gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(); | 2407 | gr_gpc0_tpc0_sm0_hww_global_esr_bpt_pause_pending_f(); |
@@ -2454,13 +2506,15 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | |||
2454 | gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(); | 2506 | gr_fecs_falcon_ecc_status_uncorrected_err_total_counter_overflow_m(); |
2455 | 2507 | ||
2456 | /* clear the interrupt */ | 2508 | /* clear the interrupt */ |
2457 | if ((corrected_delta > 0) || corrected_overflow) | 2509 | if ((corrected_delta > 0) || corrected_overflow) { |
2458 | gk20a_writel(g, | 2510 | gk20a_writel(g, |
2459 | gr_fecs_falcon_ecc_corrected_err_count_r(), 0); | 2511 | gr_fecs_falcon_ecc_corrected_err_count_r(), 0); |
2460 | if ((uncorrected_delta > 0) || uncorrected_overflow) | 2512 | } |
2513 | if ((uncorrected_delta > 0) || uncorrected_overflow) { | ||
2461 | gk20a_writel(g, | 2514 | gk20a_writel(g, |
2462 | gr_fecs_falcon_ecc_uncorrected_err_count_r(), | 2515 | gr_fecs_falcon_ecc_uncorrected_err_count_r(), |
2463 | 0); | 2516 | 0); |
2517 | } | ||
2464 | 2518 | ||
2465 | 2519 | ||
2466 | /* clear the interrupt */ | 2520 | /* clear the interrupt */ |
@@ -2481,21 +2535,26 @@ static void gr_gv11b_handle_fecs_ecc_error(struct gk20a *g, u32 intr) | |||
2481 | "fecs ecc interrupt intr: 0x%x", intr); | 2535 | "fecs ecc interrupt intr: 0x%x", intr); |
2482 | 2536 | ||
2483 | if (ecc_status & | 2537 | if (ecc_status & |
2484 | gr_fecs_falcon_ecc_status_corrected_err_imem_m()) | 2538 | gr_fecs_falcon_ecc_status_corrected_err_imem_m()) { |
2485 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); | 2539 | nvgpu_log(g, gpu_dbg_intr, "imem ecc error corrected"); |
2540 | } | ||
2486 | if (ecc_status & | 2541 | if (ecc_status & |
2487 | gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) | 2542 | gr_fecs_falcon_ecc_status_uncorrected_err_imem_m()) { |
2488 | nvgpu_log(g, gpu_dbg_intr, | 2543 | nvgpu_log(g, gpu_dbg_intr, |
2489 | "imem ecc error uncorrected"); | 2544 | "imem ecc error uncorrected"); |
2545 | } | ||
2490 | if (ecc_status & | 2546 | if (ecc_status & |
2491 | gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) | 2547 | gr_fecs_falcon_ecc_status_corrected_err_dmem_m()) { |
2492 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); | 2548 | nvgpu_log(g, gpu_dbg_intr, "dmem ecc error corrected"); |
2549 | } | ||
2493 | if (ecc_status & | 2550 | if (ecc_status & |
2494 | gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) | 2551 | gr_fecs_falcon_ecc_status_uncorrected_err_dmem_m()) { |
2495 | nvgpu_log(g, gpu_dbg_intr, | 2552 | nvgpu_log(g, gpu_dbg_intr, |
2496 | "dmem ecc error uncorrected"); | 2553 | "dmem ecc error uncorrected"); |
2497 | if (corrected_overflow || uncorrected_overflow) | 2554 | } |
2555 | if (corrected_overflow || uncorrected_overflow) { | ||
2498 | nvgpu_info(g, "fecs ecc counter overflow!"); | 2556 | nvgpu_info(g, "fecs ecc counter overflow!"); |
2557 | } | ||
2499 | 2558 | ||
2500 | nvgpu_log(g, gpu_dbg_intr, | 2559 | nvgpu_log(g, gpu_dbg_intr, |
2501 | "ecc error row address: 0x%x", | 2560 | "ecc error row address: 0x%x", |
@@ -2537,8 +2596,9 @@ int gr_gv11b_setup_rop_mapping(struct gk20a *g, struct gr_gk20a *gr) | |||
2537 | 2596 | ||
2538 | nvgpu_log_fn(g, " "); | 2597 | nvgpu_log_fn(g, " "); |
2539 | 2598 | ||
2540 | if (!gr->map_tiles) | 2599 | if (!gr->map_tiles) { |
2541 | return -1; | 2600 | return -1; |
2601 | } | ||
2542 | 2602 | ||
2543 | gk20a_writel(g, gr_crstr_map_table_cfg_r(), | 2603 | gk20a_writel(g, gr_crstr_map_table_cfg_r(), |
2544 | gr_crstr_map_table_cfg_row_offset_f(gr->map_row_offset) | | 2604 | gr_crstr_map_table_cfg_row_offset_f(gr->map_row_offset) | |
@@ -2666,8 +2726,9 @@ int gr_gv11b_init_sw_veid_bundle(struct gk20a *g) | |||
2666 | err |= gr_gk20a_wait_idle(g, | 2726 | err |= gr_gk20a_wait_idle(g, |
2667 | gk20a_get_gr_idle_timeout(g), | 2727 | gk20a_get_gr_idle_timeout(g), |
2668 | GR_IDLE_CHECK_DEFAULT); | 2728 | GR_IDLE_CHECK_DEFAULT); |
2669 | } else | 2729 | } else { |
2670 | err = gv11b_write_bundle_veid_state(g, i); | 2730 | err = gv11b_write_bundle_veid_state(g, i); |
2731 | } | ||
2671 | 2732 | ||
2672 | if (err) { | 2733 | if (err) { |
2673 | nvgpu_err(g, "failed to init sw veid bundle"); | 2734 | nvgpu_err(g, "failed to init sw veid bundle"); |
@@ -2727,8 +2788,9 @@ u32 gr_gv11b_get_nonpes_aware_tpc(struct gk20a *g, u32 gpc, u32 tpc) | |||
2727 | struct gr_gk20a *gr = &g->gr; | 2788 | struct gr_gk20a *gr = &g->gr; |
2728 | 2789 | ||
2729 | for (pes = 0; pes < gr->gpc_ppc_count[gpc]; pes++) { | 2790 | for (pes = 0; pes < gr->gpc_ppc_count[gpc]; pes++) { |
2730 | if (gr->pes_tpc_mask[pes][gpc] & BIT(tpc)) | 2791 | if (gr->pes_tpc_mask[pes][gpc] & BIT(tpc)) { |
2731 | break; | 2792 | break; |
2793 | } | ||
2732 | tpc_new += gr->pes_tpc_count[pes][gpc]; | 2794 | tpc_new += gr->pes_tpc_count[pes][gpc]; |
2733 | } | 2795 | } |
2734 | temp = (BIT(tpc) - 1) & gr->pes_tpc_mask[pes][gpc]; | 2796 | temp = (BIT(tpc) - 1) & gr->pes_tpc_mask[pes][gpc]; |
@@ -2769,8 +2831,9 @@ int gr_gv11b_load_smid_config(struct gk20a *g) | |||
2769 | int num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); | 2831 | int num_gpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_GPCS); |
2770 | 2832 | ||
2771 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); | 2833 | tpc_sm_id = nvgpu_kcalloc(g, gr_cwd_sm_id__size_1_v(), sizeof(u32)); |
2772 | if (!tpc_sm_id) | 2834 | if (!tpc_sm_id) { |
2773 | return -ENOMEM; | 2835 | return -ENOMEM; |
2836 | } | ||
2774 | 2837 | ||
2775 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ | 2838 | /* Each NV_PGRAPH_PRI_CWD_GPC_TPC_ID can store 4 TPCs.*/ |
2776 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { | 2839 | for (i = 0; i <= ((g->gr.tpc_count-1) / 4); i++) { |
@@ -2785,8 +2848,9 @@ int gr_gv11b_load_smid_config(struct gk20a *g) | |||
2785 | tpc_id = (i << 2) + j; | 2848 | tpc_id = (i << 2) + j; |
2786 | sm_id = tpc_id * sm_per_tpc; | 2849 | sm_id = tpc_id * sm_per_tpc; |
2787 | 2850 | ||
2788 | if (sm_id >= g->gr.no_of_sm) | 2851 | if (sm_id >= g->gr.no_of_sm) { |
2789 | break; | 2852 | break; |
2853 | } | ||
2790 | 2854 | ||
2791 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; | 2855 | gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index; |
2792 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; | 2856 | tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index; |
@@ -2820,12 +2884,14 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2820 | nvgpu_log_fn(g, " "); | 2884 | nvgpu_log_fn(g, " "); |
2821 | 2885 | ||
2822 | err = gv11b_alloc_subctx_header(c); | 2886 | err = gv11b_alloc_subctx_header(c); |
2823 | if (err) | 2887 | if (err) { |
2824 | return err; | 2888 | return err; |
2889 | } | ||
2825 | 2890 | ||
2826 | err = gv11b_update_subctx_header(c, gpu_va); | 2891 | err = gv11b_update_subctx_header(c, gpu_va); |
2827 | if (err) | 2892 | if (err) { |
2828 | return err; | 2893 | return err; |
2894 | } | ||
2829 | 2895 | ||
2830 | ctx = &c->ctx_header; | 2896 | ctx = &c->ctx_header; |
2831 | addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); | 2897 | addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); |
@@ -3020,8 +3086,9 @@ int gr_gv11b_init_fs_state(struct gk20a *g) | |||
3020 | } | 3086 | } |
3021 | 3087 | ||
3022 | err = gr_gk20a_init_fs_state(g); | 3088 | err = gr_gk20a_init_fs_state(g); |
3023 | if (err) | 3089 | if (err) { |
3024 | return err; | 3090 | return err; |
3091 | } | ||
3025 | 3092 | ||
3026 | g->ops.gr.load_tpc_mask(g); | 3093 | g->ops.gr.load_tpc_mask(g); |
3027 | 3094 | ||
@@ -3045,10 +3112,12 @@ void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | |||
3045 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | 3112 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, |
3046 | "sm tpc esr sm sel reg val: 0x%x", reg_val); | 3113 | "sm tpc esr sm sel reg val: 0x%x", reg_val); |
3047 | *esr_sm_sel = 0; | 3114 | *esr_sm_sel = 0; |
3048 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(reg_val)) | 3115 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm0_error_v(reg_val)) { |
3049 | *esr_sm_sel = 1; | 3116 | *esr_sm_sel = 1; |
3050 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(reg_val)) | 3117 | } |
3118 | if (gr_gpc0_tpc0_sm_tpc_esr_sm_sel_sm1_error_v(reg_val)) { | ||
3051 | *esr_sm_sel |= 1 << 1; | 3119 | *esr_sm_sel |= 1 << 1; |
3120 | } | ||
3052 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | 3121 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, |
3053 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); | 3122 | "esr_sm_sel bitmask: 0x%x", *esr_sm_sel); |
3054 | } | 3123 | } |
@@ -3154,8 +3223,9 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
3154 | int err = 0; | 3223 | int err = 0; |
3155 | 3224 | ||
3156 | tsg = tsg_gk20a_from_ch(ch); | 3225 | tsg = tsg_gk20a_from_ch(ch); |
3157 | if (!tsg) | 3226 | if (!tsg) { |
3158 | return -EINVAL; | 3227 | return -EINVAL; |
3228 | } | ||
3159 | 3229 | ||
3160 | ch_ctx = &tsg->gr_ctx; | 3230 | ch_ctx = &tsg->gr_ctx; |
3161 | 3231 | ||
@@ -3204,8 +3274,9 @@ int gv11b_gr_update_sm_error_state(struct gk20a *g, | |||
3204 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); | 3274 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask); |
3205 | } else { | 3275 | } else { |
3206 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | 3276 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); |
3207 | if (err) | 3277 | if (err) { |
3208 | goto enable_ctxsw; | 3278 | goto enable_ctxsw; |
3279 | } | ||
3209 | 3280 | ||
3210 | gr_gk20a_ctx_patch_write(g, ch_ctx, | 3281 | gr_gk20a_ctx_patch_write(g, ch_ctx, |
3211 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + | 3282 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + |
@@ -3237,14 +3308,16 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | |||
3237 | int err; | 3308 | int err; |
3238 | 3309 | ||
3239 | ops = nvgpu_kcalloc(g, g->gr.no_of_sm, sizeof(*ops)); | 3310 | ops = nvgpu_kcalloc(g, g->gr.no_of_sm, sizeof(*ops)); |
3240 | if (!ops) | 3311 | if (!ops) { |
3241 | return -ENOMEM; | 3312 | return -ENOMEM; |
3313 | } | ||
3242 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { | 3314 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { |
3243 | u32 gpc, tpc, sm; | 3315 | u32 gpc, tpc, sm; |
3244 | u32 reg_offset, reg_mask, reg_val; | 3316 | u32 reg_offset, reg_mask, reg_val; |
3245 | 3317 | ||
3246 | if (!(sms & (1 << sm_id))) | 3318 | if (!(sms & (1 << sm_id))) { |
3247 | continue; | 3319 | continue; |
3320 | } | ||
3248 | 3321 | ||
3249 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | 3322 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; |
3250 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | 3323 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; |
@@ -3282,8 +3355,9 @@ int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | |||
3282 | } | 3355 | } |
3283 | 3356 | ||
3284 | err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); | 3357 | err = gr_gk20a_exec_ctx_ops(ch, ops, i, i, 0); |
3285 | if (err) | 3358 | if (err) { |
3286 | nvgpu_err(g, "Failed to access register\n"); | 3359 | nvgpu_err(g, "Failed to access register\n"); |
3360 | } | ||
3287 | nvgpu_kfree(g, ops); | 3361 | nvgpu_kfree(g, ops); |
3288 | return err; | 3362 | return err; |
3289 | } | 3363 | } |
@@ -3372,8 +3446,9 @@ bool gv11b_gr_sm_debugger_attached(struct gk20a *g) | |||
3372 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 3446 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
3373 | "SM Debugger Mode: %d", debugger_mode); | 3447 | "SM Debugger Mode: %d", debugger_mode); |
3374 | if (debugger_mode == | 3448 | if (debugger_mode == |
3375 | gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v()) | 3449 | gr_gpc0_tpc0_sm0_dbgr_control0_debugger_mode_on_v()) { |
3376 | return true; | 3450 | return true; |
3451 | } | ||
3377 | 3452 | ||
3378 | return false; | 3453 | return false; |
3379 | } | 3454 | } |
@@ -3681,18 +3756,19 @@ static void gv11b_gr_sm_dump_warp_bpt_pause_trap_mask_regs(struct gk20a *g, | |||
3681 | offset) << 32; | 3756 | offset) << 32; |
3682 | warps_trapped |= gk20a_readl(g, | 3757 | warps_trapped |= gk20a_readl(g, |
3683 | gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() + offset); | 3758 | gr_gpc0_tpc0_sm0_dbgr_bpt_trap_mask_0_r() + offset); |
3684 | if (timeout) | 3759 | if (timeout) { |
3685 | nvgpu_err(g, | 3760 | nvgpu_err(g, |
3686 | "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " | 3761 | "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " |
3687 | "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", | 3762 | "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", |
3688 | dbgr_status0, dbgr_control0, warps_valid, | 3763 | dbgr_status0, dbgr_control0, warps_valid, |
3689 | warps_paused, warps_trapped); | 3764 | warps_paused, warps_trapped); |
3690 | else | 3765 | } else { |
3691 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 3766 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
3692 | "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " | 3767 | "STATUS0=0x%x CONTROL0=0x%x VALID_MASK=0x%llx " |
3693 | "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", | 3768 | "PAUSE_MASK=0x%llx TRAP_MASK=0x%llx\n", |
3694 | dbgr_status0, dbgr_control0, warps_valid, | 3769 | dbgr_status0, dbgr_control0, warps_valid, |
3695 | warps_paused, warps_trapped); | 3770 | warps_paused, warps_trapped); |
3771 | } | ||
3696 | } | 3772 | } |
3697 | 3773 | ||
3698 | int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, | 3774 | int gv11b_gr_wait_for_sm_lock_down(struct gk20a *g, |
@@ -3836,8 +3912,9 @@ int gr_gv11b_handle_tpc_mpc_exception(struct gk20a *g, | |||
3836 | u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() | 3912 | u32 tpc_exception = gk20a_readl(g, gr_gpc0_tpc0_tpccs_tpc_exception_r() |
3837 | + offset); | 3913 | + offset); |
3838 | 3914 | ||
3839 | if (!(tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m())) | 3915 | if (!(tpc_exception & gr_gpc0_tpc0_tpccs_tpc_exception_mpc_m())) { |
3840 | return 0; | 3916 | return 0; |
3917 | } | ||
3841 | 3918 | ||
3842 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, | 3919 | nvgpu_log(g, gpu_dbg_intr | gpu_dbg_gpu_dbg, |
3843 | "GPC%d TPC%d MPC exception", gpc, tpc); | 3920 | "GPC%d TPC%d MPC exception", gpc, tpc); |
@@ -3861,8 +3938,9 @@ static u32 _ovr_perf_regs[20] = { 0, }; | |||
3861 | 3938 | ||
3862 | void gv11b_gr_init_ovr_sm_dsm_perf(void) | 3939 | void gv11b_gr_init_ovr_sm_dsm_perf(void) |
3863 | { | 3940 | { |
3864 | if (_ovr_perf_regs[0] != 0) | 3941 | if (_ovr_perf_regs[0] != 0) { |
3865 | return; | 3942 | return; |
3943 | } | ||
3866 | 3944 | ||
3867 | _ovr_perf_regs[0] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(); | 3945 | _ovr_perf_regs[0] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(); |
3868 | _ovr_perf_regs[1] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(); | 3946 | _ovr_perf_regs[1] = gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel1_r(); |
@@ -3899,8 +3977,9 @@ static u32 _sm_dsm_perf_ctrl_regs[2]; | |||
3899 | 3977 | ||
3900 | void gv11b_gr_init_sm_dsm_reg_info(void) | 3978 | void gv11b_gr_init_sm_dsm_reg_info(void) |
3901 | { | 3979 | { |
3902 | if (_sm_dsm_perf_ctrl_regs[0] != 0) | 3980 | if (_sm_dsm_perf_ctrl_regs[0] != 0) { |
3903 | return; | 3981 | return; |
3982 | } | ||
3904 | 3983 | ||
3905 | _sm_dsm_perf_ctrl_regs[0] = | 3984 | _sm_dsm_perf_ctrl_regs[0] = |
3906 | gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(); | 3985 | gr_egpc0_etpc0_sm_dsm_perf_counter_control0_r(); |
@@ -4045,8 +4124,9 @@ bool gv11b_gr_pri_is_etpc_addr(struct gk20a *g, u32 addr) | |||
4045 | 4124 | ||
4046 | if (g->ops.gr.is_egpc_addr(g, addr)) { | 4125 | if (g->ops.gr.is_egpc_addr(g, addr)) { |
4047 | egpc_addr = pri_gpccs_addr_mask(addr); | 4126 | egpc_addr = pri_gpccs_addr_mask(addr); |
4048 | if (g->ops.gr.is_tpc_addr(g, egpc_addr)) | 4127 | if (g->ops.gr.is_tpc_addr(g, egpc_addr)) { |
4049 | return true; | 4128 | return true; |
4129 | } | ||
4050 | } | 4130 | } |
4051 | 4131 | ||
4052 | return false; | 4132 | return false; |
@@ -4061,8 +4141,9 @@ static u32 pri_get_egpc_num(struct gk20a *g, u32 addr) | |||
4061 | 4141 | ||
4062 | for (i = 0; i < num_gpcs; i++) { | 4142 | for (i = 0; i < num_gpcs; i++) { |
4063 | start = egpc_base + (i * gpc_stride); | 4143 | start = egpc_base + (i * gpc_stride); |
4064 | if ((addr >= start) && (addr < (start + gpc_stride))) | 4144 | if ((addr >= start) && (addr < (start + gpc_stride))) { |
4065 | return i; | 4145 | return i; |
4146 | } | ||
4066 | } | 4147 | } |
4067 | return 0; | 4148 | return 0; |
4068 | } | 4149 | } |
@@ -4134,8 +4215,9 @@ int gv11b_gr_decode_egpc_addr(struct gk20a *g, u32 addr, | |||
4134 | nvgpu_log_info(g, "tpc=0x%x", *tpc_num); | 4215 | nvgpu_log_info(g, "tpc=0x%x", *tpc_num); |
4135 | } | 4216 | } |
4136 | tpc_addr = pri_tpccs_addr_mask(addr); | 4217 | tpc_addr = pri_tpccs_addr_mask(addr); |
4137 | if (pri_is_smpc_addr_in_etpc_shared(g, tpc_addr)) | 4218 | if (pri_is_smpc_addr_in_etpc_shared(g, tpc_addr)) { |
4138 | *broadcast_flags |= PRI_BROADCAST_FLAGS_SMPC; | 4219 | *broadcast_flags |= PRI_BROADCAST_FLAGS_SMPC; |
4220 | } | ||
4139 | } | 4221 | } |
4140 | 4222 | ||
4141 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | 4223 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, |
@@ -4213,8 +4295,9 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, | |||
4213 | 4295 | ||
4214 | gpc_addr = pri_gpccs_addr_mask(priv_addr); | 4296 | gpc_addr = pri_gpccs_addr_mask(priv_addr); |
4215 | tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); | 4297 | tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); |
4216 | if (tpc_num >= g->gr.gpc_tpc_count[gpc_num]) | 4298 | if (tpc_num >= g->gr.gpc_tpc_count[gpc_num]) { |
4217 | continue; | 4299 | continue; |
4300 | } | ||
4218 | 4301 | ||
4219 | priv_addr_table[*t] = priv_addr; | 4302 | priv_addr_table[*t] = priv_addr; |
4220 | nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", | 4303 | nvgpu_log_info(g, "priv_addr_table[%d]:%#08x", |
@@ -4229,11 +4312,11 @@ void gv11b_gr_egpc_etpc_priv_addr_table(struct gk20a *g, u32 addr, | |||
4229 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; | 4312 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; |
4230 | tpc_num++) { | 4313 | tpc_num++) { |
4231 | if (broadcast_flags & | 4314 | if (broadcast_flags & |
4232 | PRI_BROADCAST_FLAGS_SMPC) | 4315 | PRI_BROADCAST_FLAGS_SMPC) { |
4233 | gv11b_gr_update_priv_addr_table_smpc( | 4316 | gv11b_gr_update_priv_addr_table_smpc( |
4234 | g, gpc_num, tpc_num, addr, | 4317 | g, gpc_num, tpc_num, addr, |
4235 | priv_addr_table, t); | 4318 | priv_addr_table, t); |
4236 | else { | 4319 | } else { |
4237 | priv_addr_table[*t] = | 4320 | priv_addr_table[*t] = |
4238 | pri_etpc_addr(g, | 4321 | pri_etpc_addr(g, |
4239 | pri_tpccs_addr_mask(addr), | 4322 | pri_tpccs_addr_mask(addr), |
@@ -4304,10 +4387,11 @@ int gr_gv11b_init_preemption_state(struct gk20a *g) | |||
4304 | 4387 | ||
4305 | nvgpu_log_fn(g, " "); | 4388 | nvgpu_log_fn(g, " "); |
4306 | 4389 | ||
4307 | if (gr->gfxp_wfi_timeout_unit == GFXP_WFI_TIMEOUT_UNIT_USEC) | 4390 | if (gr->gfxp_wfi_timeout_unit == GFXP_WFI_TIMEOUT_UNIT_USEC) { |
4308 | unit = gr_debug_2_gfxp_wfi_timeout_unit_usec_f(); | 4391 | unit = gr_debug_2_gfxp_wfi_timeout_unit_usec_f(); |
4309 | else | 4392 | } else { |
4310 | unit = gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f(); | 4393 | unit = gr_debug_2_gfxp_wfi_timeout_unit_sysclk_f(); |
4394 | } | ||
4311 | 4395 | ||
4312 | debug_2 = gk20a_readl(g, gr_debug_2_r()); | 4396 | debug_2 = gk20a_readl(g, gr_debug_2_r()); |
4313 | debug_2 = set_field(debug_2, | 4397 | debug_2 = set_field(debug_2, |
@@ -4326,12 +4410,13 @@ void gr_gv11b_init_gfxp_wfi_timeout_count(struct gk20a *g) | |||
4326 | 4410 | ||
4327 | unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g) | 4411 | unsigned long gr_gv11b_get_max_gfxp_wfi_timeout_count(struct gk20a *g) |
4328 | { | 4412 | { |
4329 | if (g->gr.gfxp_wfi_timeout_unit == GFXP_WFI_TIMEOUT_UNIT_USEC) | 4413 | if (g->gr.gfxp_wfi_timeout_unit == GFXP_WFI_TIMEOUT_UNIT_USEC) { |
4330 | /* 100 msec in usec count */ | 4414 | /* 100 msec in usec count */ |
4331 | return (100UL * 1000UL); | 4415 | return (100UL * 1000UL); |
4332 | else | 4416 | } else { |
4333 | /* 100 msec for 1GHz clock */ | 4417 | /* 100 msec for 1GHz clock */ |
4334 | return (100UL * 1000UL * 1000UL); | 4418 | return (100UL * 1000UL * 1000UL); |
4419 | } | ||
4335 | } | 4420 | } |
4336 | 4421 | ||
4337 | static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, | 4422 | static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, |
@@ -4355,11 +4440,13 @@ static int gr_gv11b_ecc_scrub_is_done(struct gk20a *g, | |||
4355 | 4440 | ||
4356 | do { | 4441 | do { |
4357 | val = gk20a_readl(g, gpc_offset + tpc_offset + scrub_reg); | 4442 | val = gk20a_readl(g, gpc_offset + tpc_offset + scrub_reg); |
4358 | if ((val & scrub_mask) == scrub_done) | 4443 | if ((val & scrub_mask) == scrub_done) { |
4359 | break; | 4444 | break; |
4445 | } | ||
4360 | 4446 | ||
4361 | if (nvgpu_timeout_expired(&timeout)) | 4447 | if (nvgpu_timeout_expired(&timeout)) { |
4362 | return -ETIMEDOUT; | 4448 | return -ETIMEDOUT; |
4449 | } | ||
4363 | 4450 | ||
4364 | nvgpu_udelay(ECC_SCRUBBING_TIMEOUT_DEFAULT); | 4451 | nvgpu_udelay(ECC_SCRUBBING_TIMEOUT_DEFAULT); |
4365 | } while (1); | 4452 | } while (1); |
@@ -4629,16 +4716,21 @@ void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) | |||
4629 | 4716 | ||
4630 | gr_gv11b_detect_ecc_enabled_units(g); | 4717 | gr_gv11b_detect_ecc_enabled_units(g); |
4631 | 4718 | ||
4632 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) | 4719 | if (gr_gv11b_ecc_scrub_sm_lrf(g)) { |
4633 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); | 4720 | nvgpu_warn(g, "ECC SCRUB SM LRF Failed"); |
4634 | if (gr_gv11b_ecc_scrub_sm_l1_data(g)) | 4721 | } |
4722 | if (gr_gv11b_ecc_scrub_sm_l1_data(g)) { | ||
4635 | nvgpu_warn(g, "ECC SCRUB SM L1 DATA Failed"); | 4723 | nvgpu_warn(g, "ECC SCRUB SM L1 DATA Failed"); |
4636 | if (gr_gv11b_ecc_scrub_sm_l1_tag(g)) | 4724 | } |
4725 | if (gr_gv11b_ecc_scrub_sm_l1_tag(g)) { | ||
4637 | nvgpu_warn(g, "ECC SCRUB SM L1 TAG Failed"); | 4726 | nvgpu_warn(g, "ECC SCRUB SM L1 TAG Failed"); |
4638 | if (gr_gv11b_ecc_scrub_sm_cbu(g)) | 4727 | } |
4728 | if (gr_gv11b_ecc_scrub_sm_cbu(g)) { | ||
4639 | nvgpu_warn(g, "ECC SCRUB SM CBU Failed"); | 4729 | nvgpu_warn(g, "ECC SCRUB SM CBU Failed"); |
4640 | if (gr_gv11b_ecc_scrub_sm_icahe(g)) | 4730 | } |
4731 | if (gr_gv11b_ecc_scrub_sm_icahe(g)) { | ||
4641 | nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); | 4732 | nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); |
4733 | } | ||
4642 | 4734 | ||
4643 | } | 4735 | } |
4644 | 4736 | ||
@@ -4689,8 +4781,9 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | |||
4689 | if (pri_is_gpc_addr_shared(g, addr)) { | 4781 | if (pri_is_gpc_addr_shared(g, addr)) { |
4690 | *addr_type = CTXSW_ADDR_TYPE_GPC; | 4782 | *addr_type = CTXSW_ADDR_TYPE_GPC; |
4691 | *broadcast_flags |= PRI_BROADCAST_FLAGS_GPC; | 4783 | *broadcast_flags |= PRI_BROADCAST_FLAGS_GPC; |
4692 | } else | 4784 | } else { |
4693 | *gpc_num = pri_get_gpc_num(g, addr); | 4785 | *gpc_num = pri_get_gpc_num(g, addr); |
4786 | } | ||
4694 | 4787 | ||
4695 | if (pri_is_ppc_addr(g, gpc_addr)) { | 4788 | if (pri_is_ppc_addr(g, gpc_addr)) { |
4696 | *addr_type = CTXSW_ADDR_TYPE_PPC; | 4789 | *addr_type = CTXSW_ADDR_TYPE_PPC; |
@@ -4718,10 +4811,11 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr, | |||
4718 | return 0; | 4811 | return 0; |
4719 | } else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) { | 4812 | } else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) { |
4720 | *addr_type = CTXSW_ADDR_TYPE_LTCS; | 4813 | *addr_type = CTXSW_ADDR_TYPE_LTCS; |
4721 | if (g->ops.ltc.is_ltcs_ltss_addr(g, addr)) | 4814 | if (g->ops.ltc.is_ltcs_ltss_addr(g, addr)) { |
4722 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS; | 4815 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS; |
4723 | else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr)) | 4816 | } else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr)) { |
4724 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS; | 4817 | *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS; |
4818 | } | ||
4725 | return 0; | 4819 | return 0; |
4726 | } else if (pri_is_fbpa_addr(g, addr)) { | 4820 | } else if (pri_is_fbpa_addr(g, addr)) { |
4727 | *addr_type = CTXSW_ADDR_TYPE_FBPA; | 4821 | *addr_type = CTXSW_ADDR_TYPE_FBPA; |
@@ -4830,8 +4924,9 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4830 | &gpc_num, &tpc_num, &ppc_num, &be_num, | 4924 | &gpc_num, &tpc_num, &ppc_num, &be_num, |
4831 | &broadcast_flags); | 4925 | &broadcast_flags); |
4832 | nvgpu_log(g, gpu_dbg_gpu_dbg, "addr_type = %d", addr_type); | 4926 | nvgpu_log(g, gpu_dbg_gpu_dbg, "addr_type = %d", addr_type); |
4833 | if (err) | 4927 | if (err) { |
4834 | return err; | 4928 | return err; |
4929 | } | ||
4835 | 4930 | ||
4836 | if ((addr_type == CTXSW_ADDR_TYPE_SYS) || | 4931 | if ((addr_type == CTXSW_ADDR_TYPE_SYS) || |
4837 | (addr_type == CTXSW_ADDR_TYPE_BE)) { | 4932 | (addr_type == CTXSW_ADDR_TYPE_BE)) { |
@@ -4841,10 +4936,11 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4841 | * so that we can look up the offset | 4936 | * so that we can look up the offset |
4842 | */ | 4937 | */ |
4843 | if ((addr_type == CTXSW_ADDR_TYPE_BE) && | 4938 | if ((addr_type == CTXSW_ADDR_TYPE_BE) && |
4844 | !(broadcast_flags & PRI_BROADCAST_FLAGS_BE)) | 4939 | !(broadcast_flags & PRI_BROADCAST_FLAGS_BE)) { |
4845 | priv_addr_table[t++] = pri_be_shared_addr(g, addr); | 4940 | priv_addr_table[t++] = pri_be_shared_addr(g, addr); |
4846 | else | 4941 | } else { |
4847 | priv_addr_table[t++] = addr; | 4942 | priv_addr_table[t++] = addr; |
4943 | } | ||
4848 | 4944 | ||
4849 | *num_registers = t; | 4945 | *num_registers = t; |
4850 | return 0; | 4946 | return 0; |
@@ -4858,7 +4954,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4858 | if (broadcast_flags & PRI_BROADCAST_FLAGS_GPC) { | 4954 | if (broadcast_flags & PRI_BROADCAST_FLAGS_GPC) { |
4859 | for (gpc_num = 0; gpc_num < g->gr.gpc_count; gpc_num++) { | 4955 | for (gpc_num = 0; gpc_num < g->gr.gpc_count; gpc_num++) { |
4860 | 4956 | ||
4861 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) | 4957 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) { |
4862 | for (tpc_num = 0; | 4958 | for (tpc_num = 0; |
4863 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; | 4959 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; |
4864 | tpc_num++) { | 4960 | tpc_num++) { |
@@ -4867,12 +4963,14 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4867 | pri_tpccs_addr_mask(addr), | 4963 | pri_tpccs_addr_mask(addr), |
4868 | gpc_num, tpc_num); | 4964 | gpc_num, tpc_num); |
4869 | } | 4965 | } |
4966 | } | ||
4870 | 4967 | ||
4871 | else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) { | 4968 | else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) { |
4872 | err = gr_gk20a_split_ppc_broadcast_addr(g, | 4969 | err = gr_gk20a_split_ppc_broadcast_addr(g, |
4873 | addr, gpc_num, priv_addr_table, &t); | 4970 | addr, gpc_num, priv_addr_table, &t); |
4874 | if (err) | 4971 | if (err) { |
4875 | return err; | 4972 | return err; |
4973 | } | ||
4876 | } else { | 4974 | } else { |
4877 | priv_addr = pri_gpc_addr(g, | 4975 | priv_addr = pri_gpc_addr(g, |
4878 | pri_gpccs_addr_mask(addr), | 4976 | pri_gpccs_addr_mask(addr), |
@@ -4880,8 +4978,9 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4880 | 4978 | ||
4881 | gpc_addr = pri_gpccs_addr_mask(priv_addr); | 4979 | gpc_addr = pri_gpccs_addr_mask(priv_addr); |
4882 | tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); | 4980 | tpc_num = g->ops.gr.get_tpc_num(g, gpc_addr); |
4883 | if (tpc_num >= g->gr.gpc_tpc_count[gpc_num]) | 4981 | if (tpc_num >= g->gr.gpc_tpc_count[gpc_num]) { |
4884 | continue; | 4982 | continue; |
4983 | } | ||
4885 | 4984 | ||
4886 | priv_addr_table[t++] = priv_addr; | 4985 | priv_addr_table[t++] = priv_addr; |
4887 | } | 4986 | } |
@@ -4963,7 +5062,7 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4963 | priv_addr_table, &t, | 5062 | priv_addr_table, &t, |
4964 | domain_start, 1); | 5063 | domain_start, 1); |
4965 | } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_GPC)) { | 5064 | } else if (!(broadcast_flags & PRI_BROADCAST_FLAGS_GPC)) { |
4966 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) | 5065 | if (broadcast_flags & PRI_BROADCAST_FLAGS_TPC) { |
4967 | for (tpc_num = 0; | 5066 | for (tpc_num = 0; |
4968 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; | 5067 | tpc_num < g->gr.gpc_tpc_count[gpc_num]; |
4969 | tpc_num++) { | 5068 | tpc_num++) { |
@@ -4972,11 +5071,12 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g, | |||
4972 | pri_tpccs_addr_mask(addr), | 5071 | pri_tpccs_addr_mask(addr), |
4973 | gpc_num, tpc_num); | 5072 | gpc_num, tpc_num); |
4974 | } | 5073 | } |
4975 | else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) | 5074 | } else if (broadcast_flags & PRI_BROADCAST_FLAGS_PPC) { |
4976 | err = gr_gk20a_split_ppc_broadcast_addr(g, | 5075 | err = gr_gk20a_split_ppc_broadcast_addr(g, |
4977 | addr, gpc_num, priv_addr_table, &t); | 5076 | addr, gpc_num, priv_addr_table, &t); |
4978 | else | 5077 | } else { |
4979 | priv_addr_table[t++] = addr; | 5078 | priv_addr_table[t++] = addr; |
5079 | } | ||
4980 | } | 5080 | } |
4981 | 5081 | ||
4982 | *num_registers = t; | 5082 | *num_registers = t; |