diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/Makefile | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 135 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 24 |
5 files changed, 166 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/Makefile b/drivers/gpu/nvgpu/gp10b/Makefile index 64cd4179..722cc550 100644 --- a/drivers/gpu/nvgpu/gp10b/Makefile +++ b/drivers/gpu/nvgpu/gp10b/Makefile | |||
@@ -10,4 +10,5 @@ ccflags-$(CONFIG_GK20A) += -Wno-multichar | |||
10 | 10 | ||
11 | obj-$(CONFIG_GK20A) += \ | 11 | obj-$(CONFIG_GK20A) += \ |
12 | gr_gp10b.o \ | 12 | gr_gp10b.o \ |
13 | mc_gp10b.o \ | ||
13 | hal_gp10b.o | 14 | hal_gp10b.o |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 61bae5c7..235254c8 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -21,6 +21,7 @@ | |||
21 | #include "gk20a/gk20a.h" | 21 | #include "gk20a/gk20a.h" |
22 | 22 | ||
23 | #include "gp10b/gr_gp10b.h" | 23 | #include "gp10b/gr_gp10b.h" |
24 | #include "gp10b/mc_gp10b.h" | ||
24 | 25 | ||
25 | #include "gm20b/ltc_gm20b.h" | 26 | #include "gm20b/ltc_gm20b.h" |
26 | #include "gm20b/fb_gm20b.h" | 27 | #include "gm20b/fb_gm20b.h" |
@@ -83,6 +84,7 @@ struct gpu_ops gp10b_ops = { | |||
83 | int gp10b_init_hal(struct gpu_ops *gops) | 84 | int gp10b_init_hal(struct gpu_ops *gops) |
84 | { | 85 | { |
85 | *gops = gp10b_ops; | 86 | *gops = gp10b_ops; |
87 | gp10b_init_mc(gops); | ||
86 | gm20b_init_ltc(gops); | 88 | gm20b_init_ltc(gops); |
87 | gp10b_init_gr(gops); | 89 | gp10b_init_gr(gops); |
88 | gm20b_init_ltc(gops); | 90 | gm20b_init_ltc(gops); |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h index ba0af497..21c592da 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_mc_gp10b.h | |||
@@ -78,6 +78,10 @@ static inline u32 mc_intr_pfifo_pending_f(void) | |||
78 | { | 78 | { |
79 | return 0x100; | 79 | return 0x100; |
80 | } | 80 | } |
81 | static inline u32 mc_intr_pgraph_pending_f(void) | ||
82 | { | ||
83 | return 0x1000; | ||
84 | } | ||
81 | static inline u32 mc_intr_pmu_pending_f(void) | 85 | static inline u32 mc_intr_pmu_pending_f(void) |
82 | { | 86 | { |
83 | return 0x1000000; | 87 | return 0x1000000; |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c new file mode 100644 index 00000000..cdafaf56 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -0,0 +1,135 @@ | |||
1 | /* | ||
2 | * GP20B master | ||
3 | * | ||
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | */ | ||
15 | |||
16 | #include <linux/types.h> | ||
17 | |||
18 | #include "gk20a/gk20a.h" | ||
19 | #include "mc_gp10b.h" | ||
20 | #include "hw_mc_gp10b.h" | ||
21 | |||
22 | void mc_gp10b_intr_enable(struct gk20a *g) | ||
23 | { | ||
24 | if (!tegra_platform_is_linsim()) { | ||
25 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); | ||
26 | gk20a_writel(g, mc_intr_en_set_r(0), | ||
27 | mc_intr_pfifo_pending_f() | ||
28 | | mc_intr_pgraph_pending_f()); | ||
29 | gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); | ||
30 | gk20a_writel(g, mc_intr_en_set_r(1), | ||
31 | mc_intr_pfifo_pending_f() | ||
32 | | mc_intr_pgraph_pending_f() | ||
33 | | mc_intr_priv_ring_pending_f() | ||
34 | | mc_intr_ltc_pending_f() | ||
35 | | mc_intr_pbus_pending_f()); | ||
36 | } | ||
37 | } | ||
38 | |||
39 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) | ||
40 | { | ||
41 | u32 mc_intr_0; | ||
42 | |||
43 | if (!g->power_on) | ||
44 | return IRQ_NONE; | ||
45 | |||
46 | /* not from gpu when sharing irq with others */ | ||
47 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
48 | if (unlikely(!mc_intr_0)) | ||
49 | return IRQ_NONE; | ||
50 | |||
51 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); | ||
52 | |||
53 | return IRQ_WAKE_THREAD; | ||
54 | } | ||
55 | |||
56 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | ||
57 | { | ||
58 | u32 mc_intr_1; | ||
59 | |||
60 | if (!g->power_on) | ||
61 | return IRQ_NONE; | ||
62 | |||
63 | /* not from gpu when sharing irq with others */ | ||
64 | mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); | ||
65 | if (unlikely(!mc_intr_1)) | ||
66 | return IRQ_NONE; | ||
67 | |||
68 | gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); | ||
69 | |||
70 | return IRQ_WAKE_THREAD; | ||
71 | } | ||
72 | |||
73 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | ||
74 | { | ||
75 | u32 mc_intr_0; | ||
76 | |||
77 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | ||
78 | |||
79 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | ||
80 | |||
81 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | ||
82 | |||
83 | if (mc_intr_0 & mc_intr_pgraph_pending_f()) | ||
84 | gr_gk20a_elpg_protected_call(g, gk20a_gr_isr(g)); | ||
85 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | ||
86 | gk20a_fifo_isr(g); | ||
87 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | ||
88 | gk20a_pmu_isr(g); | ||
89 | if (mc_intr_0 & mc_intr_priv_ring_pending_f()) | ||
90 | gk20a_priv_ring_isr(g); | ||
91 | if (mc_intr_0 & mc_intr_ltc_pending_f()) | ||
92 | g->ops.ltc.isr(g); | ||
93 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | ||
94 | gk20a_pbus_isr(g); | ||
95 | |||
96 | gk20a_writel(g, mc_intr_en_set_r(0), | ||
97 | mc_intr_pfifo_pending_f() | ||
98 | | mc_intr_pgraph_pending_f()); | ||
99 | |||
100 | return IRQ_HANDLED; | ||
101 | } | ||
102 | |||
103 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | ||
104 | { | ||
105 | u32 mc_intr_1; | ||
106 | |||
107 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | ||
108 | |||
109 | mc_intr_1 = gk20a_readl(g, mc_intr_r(1)); | ||
110 | |||
111 | gk20a_dbg(gpu_dbg_intr, "non-stall intr %08x\n", mc_intr_1); | ||
112 | |||
113 | if (mc_intr_1 & mc_intr_pfifo_pending_f()) | ||
114 | gk20a_fifo_nonstall_isr(g); | ||
115 | if (mc_intr_1 & mc_intr_pgraph_pending_f()) | ||
116 | gk20a_gr_nonstall_isr(g); | ||
117 | |||
118 | gk20a_writel(g, mc_intr_en_set_r(1), | ||
119 | mc_intr_pfifo_pending_f() | ||
120 | | mc_intr_pgraph_pending_f() | ||
121 | | mc_intr_priv_ring_pending_f() | ||
122 | | mc_intr_ltc_pending_f() | ||
123 | | mc_intr_pbus_pending_f()); | ||
124 | |||
125 | return IRQ_HANDLED; | ||
126 | } | ||
127 | |||
128 | void gp10b_init_mc(struct gpu_ops *gops) | ||
129 | { | ||
130 | gops->mc.intr_enable = mc_gp10b_intr_enable; | ||
131 | gops->mc.isr_stall = mc_gp10b_isr_stall; | ||
132 | gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; | ||
133 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; | ||
134 | gops->mc.isr_thread_nonstall = mc_gp10b_intr_thread_nonstall; | ||
135 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h new file mode 100644 index 00000000..f274ce05 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h | |||
@@ -0,0 +1,24 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef MC_GP20B_H | ||
15 | #define MC_GP20B_H | ||
16 | struct gk20a; | ||
17 | |||
18 | void gp10b_init_mc(struct gpu_ops *gops); | ||
19 | void mc_gp10b_intr_enable(struct gk20a *g); | ||
20 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); | ||
21 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); | ||
22 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); | ||
23 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g); | ||
24 | #endif | ||