diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/common/sim_pci.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/common/sim_pci.c b/drivers/gpu/nvgpu/common/sim_pci.c index 2f6f6765..b05504fe 100644 --- a/drivers/gpu/nvgpu/common/sim_pci.c +++ b/drivers/gpu/nvgpu/common/sim_pci.c | |||
@@ -89,11 +89,11 @@ static int rpc_send_message(struct gk20a *g) | |||
89 | sim_dma_target_phys_pci_coherent_f() | | 89 | sim_dma_target_phys_pci_coherent_f() | |
90 | sim_dma_status_valid_f() | | 90 | sim_dma_status_valid_f() | |
91 | sim_dma_size_4kb_f() | | 91 | sim_dma_size_4kb_f() | |
92 | sim_dma_addr_lo_f(nvgpu_mem_get_addr(g, &g->sim->msg_bfr) | 92 | sim_dma_addr_lo_f(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr) |
93 | >> PAGE_SHIFT); | 93 | >> PAGE_SHIFT); |
94 | 94 | ||
95 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = | 95 | *sim_send_ring_bfr(g, dma_hi_offset*sizeof(u32)) = |
96 | u64_hi32(nvgpu_mem_get_addr(g, &g->sim->msg_bfr)); | 96 | u64_hi32(nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)); |
97 | 97 | ||
98 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; | 98 | *sim_msg_hdr(g, sim_msg_sequence_r()) = g->sim->sequence_base++; |
99 | 99 | ||
@@ -138,7 +138,8 @@ static int rpc_recv_poll(struct gk20a *g) | |||
138 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | | 138 | recv_phys_addr = (u64)recv_phys_addr_hi << 32 | |
139 | (u64)recv_phys_addr_lo << PAGE_SHIFT; | 139 | (u64)recv_phys_addr_lo << PAGE_SHIFT; |
140 | 140 | ||
141 | if (recv_phys_addr != nvgpu_mem_get_addr(g, &g->sim->msg_bfr)) { | 141 | if (recv_phys_addr != |
142 | nvgpu_mem_get_phys_addr(g, &g->sim->msg_bfr)) { | ||
142 | nvgpu_err(g, "Error in RPC reply"); | 143 | nvgpu_err(g, "Error in RPC reply"); |
143 | return -EINVAL; | 144 | return -EINVAL; |
144 | } | 145 | } |
@@ -217,7 +218,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) | |||
217 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); | 218 | sim_writel(g->sim, sim_send_put_r(), g->sim->send_ring_put); |
218 | 219 | ||
219 | /* write send ring address and make it valid */ | 220 | /* write send ring address and make it valid */ |
220 | phys = nvgpu_mem_get_addr(g, &g->sim->send_bfr); | 221 | phys = nvgpu_mem_get_phys_addr(g, &g->sim->send_bfr); |
221 | sim_writel(g->sim, sim_send_ring_hi_r(), | 222 | sim_writel(g->sim, sim_send_ring_hi_r(), |
222 | sim_send_ring_hi_addr_f(u64_hi32(phys))); | 223 | sim_send_ring_hi_addr_f(u64_hi32(phys))); |
223 | sim_writel(g->sim, sim_send_ring_r(), | 224 | sim_writel(g->sim, sim_send_ring_r(), |
@@ -234,7 +235,7 @@ static void nvgpu_sim_init_late(struct gk20a *g) | |||
234 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); | 235 | sim_writel(g->sim, sim_recv_get_r(), g->sim->recv_ring_get); |
235 | 236 | ||
236 | /* write send ring address and make it valid */ | 237 | /* write send ring address and make it valid */ |
237 | phys = nvgpu_mem_get_addr(g, &g->sim->recv_bfr); | 238 | phys = nvgpu_mem_get_phys_addr(g, &g->sim->recv_bfr); |
238 | sim_writel(g->sim, sim_recv_ring_hi_r(), | 239 | sim_writel(g->sim, sim_recv_ring_hi_r(), |
239 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); | 240 | sim_recv_ring_hi_addr_f(u64_hi32(phys))); |
240 | sim_writel(g->sim, sim_recv_ring_r(), | 241 | sim_writel(g->sim, sim_recv_ring_r(), |