2 files changed, 12 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 84bb3646..a2ecd864 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -541,7 +541,11 @@ static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g,
 int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
 {
         struct fifo_gk20a *f = &g->fifo;
-        struct channel_gk20a *ch = &f->channel[info->chid];
+        struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]);
+
+        gk20a_dbg_fn("");
+        if (!ch)
+                return 0;
 
         gk20a_err(dev_from_gk20a(g), "fifo intr (%d) on ch %u",
                 info->type, info->chid);
@@ -555,14 +559,15 @@ int vgpu_fifo_isr(struct gk20a *g, struct tegra_vgpu_fifo_intr_info *info)
                                         NVGPU_CHANNEL_FIFO_ERROR_IDLE_TIMEOUT);
                 break;
         case TEGRA_VGPU_FIFO_INTR_MMU_FAULT:
-                gk20a_channel_abort(ch);
                 vgpu_fifo_set_ctx_mmu_error(g, ch);
+                gk20a_channel_abort(ch);
                 break;
         default:
                 WARN_ON(1);
                 break;
         }
 
+        gk20a_channel_put(ch);
         return 0;
 }
 
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 7dfc970e..b259a0c3 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -851,9 +851,12 @@ int vgpu_init_gr_support(struct gk20a *g)
 int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
 {
         struct fifo_gk20a *f = &g->fifo;
-        struct channel_gk20a *ch = &f->channel[info->chid];
+        struct channel_gk20a *ch = gk20a_channel_get(&f->channel[info->chid]);
 
         gk20a_dbg_fn("");
+        if (!ch)
+                return 0;
+
         if (info->type != TEGRA_VGPU_GR_INTR_NOTIFY &&
                 info->type != TEGRA_VGPU_GR_INTR_SEMAPHORE)
                 gk20a_err(dev_from_gk20a(g), "gr intr (%d) on ch %u",
@@ -899,6 +902,7 @@ int vgpu_gr_isr(struct gk20a *g, struct tegra_vgpu_gr_intr_info *info)
                 break;
         }
 
+        gk20a_channel_put(ch);
         return 0;
 }