diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/driver_common.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/sysfs.c | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu_fw.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | 61 |
8 files changed, 130 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/common/linux/driver_common.c b/drivers/gpu/nvgpu/common/linux/driver_common.c index c3663117..53789423 100644 --- a/drivers/gpu/nvgpu/common/linux/driver_common.c +++ b/drivers/gpu/nvgpu/common/linux/driver_common.c | |||
@@ -159,6 +159,7 @@ static void nvgpu_init_pm_vars(struct gk20a *g) | |||
159 | g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g)); | 159 | g->support_pmu = support_gk20a_pmu(dev_from_gk20a(g)); |
160 | g->can_railgate = platform->can_railgate_init; | 160 | g->can_railgate = platform->can_railgate_init; |
161 | g->railgate_delay = platform->railgate_delay_init; | 161 | g->railgate_delay = platform->railgate_delay_init; |
162 | g->ldiv_slowdown_factor = platform->ldiv_slowdown_factor_init; | ||
162 | __nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon); | 163 | __nvgpu_set_enabled(g, NVGPU_PMU_PERFMON, platform->enable_perfmon); |
163 | 164 | ||
164 | /* set default values to aelpg parameters */ | 165 | /* set default values to aelpg parameters */ |
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h index 43afbbf9..dec79b87 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gk20a.h +++ b/drivers/gpu/nvgpu/common/linux/platform_gk20a.h | |||
@@ -74,6 +74,9 @@ struct gk20a_platform { | |||
74 | /* Delay before rail gated */ | 74 | /* Delay before rail gated */ |
75 | int railgate_delay_init; | 75 | int railgate_delay_init; |
76 | 76 | ||
77 | /* init value for slowdown factor */ | ||
78 | u8 ldiv_slowdown_factor_init; | ||
79 | |||
77 | /* Second Level Clock Gating: true = enable false = disable */ | 80 | /* Second Level Clock Gating: true = enable false = disable */ |
78 | bool enable_slcg; | 81 | bool enable_slcg; |
79 | 82 | ||
diff --git a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c index 96acf24b..6e54d00b 100644 --- a/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c +++ b/drivers/gpu/nvgpu/common/linux/platform_gp10b_tegra.c | |||
@@ -370,6 +370,9 @@ struct gk20a_platform gp10b_tegra_platform = { | |||
370 | /* power management configuration */ | 370 | /* power management configuration */ |
371 | .railgate_delay_init = 500, | 371 | .railgate_delay_init = 500, |
372 | 372 | ||
373 | /* ldiv slowdown factor */ | ||
374 | .ldiv_slowdown_factor_init = SLOWDOWN_FACTOR_FPDIV_BY16, | ||
375 | |||
373 | /* power management configuration */ | 376 | /* power management configuration */ |
374 | .can_railgate_init = true, | 377 | .can_railgate_init = true, |
375 | .enable_elpg = true, | 378 | .enable_elpg = true, |
diff --git a/drivers/gpu/nvgpu/common/linux/sysfs.c b/drivers/gpu/nvgpu/common/linux/sysfs.c index 6709285d..1f6da803 100644 --- a/drivers/gpu/nvgpu/common/linux/sysfs.c +++ b/drivers/gpu/nvgpu/common/linux/sysfs.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -504,6 +504,58 @@ static ssize_t elpg_enable_read(struct device *dev, | |||
504 | 504 | ||
505 | static DEVICE_ATTR(elpg_enable, ROOTRW, elpg_enable_read, elpg_enable_store); | 505 | static DEVICE_ATTR(elpg_enable, ROOTRW, elpg_enable_read, elpg_enable_store); |
506 | 506 | ||
507 | static ssize_t ldiv_slowdown_factor_store(struct device *dev, | ||
508 | struct device_attribute *attr, const char *buf, size_t count) | ||
509 | { | ||
510 | struct gk20a *g = get_gk20a(dev); | ||
511 | unsigned long val = 0; | ||
512 | int err; | ||
513 | |||
514 | if (kstrtoul(buf, 10, &val) < 0) { | ||
515 | nvgpu_err(g, "parse error for input SLOWDOWN factor\n"); | ||
516 | return -EINVAL; | ||
517 | } | ||
518 | |||
519 | if (val >= SLOWDOWN_FACTOR_FPDIV_BYMAX) { | ||
520 | nvgpu_err(g, "Invalid SLOWDOWN factor\n"); | ||
521 | return -EINVAL; | ||
522 | } | ||
523 | |||
524 | if (val == g->ldiv_slowdown_factor) | ||
525 | return count; | ||
526 | |||
527 | if (!g->power_on) { | ||
528 | g->ldiv_slowdown_factor = val; | ||
529 | } else { | ||
530 | err = gk20a_busy(g); | ||
531 | if (err) | ||
532 | return -EAGAIN; | ||
533 | |||
534 | g->ldiv_slowdown_factor = val; | ||
535 | |||
536 | if (g->ops.pmu.pmu_pg_init_param) | ||
537 | g->ops.pmu.pmu_pg_init_param(g, | ||
538 | PMU_PG_ELPG_ENGINE_ID_GRAPHICS); | ||
539 | |||
540 | gk20a_idle(g); | ||
541 | } | ||
542 | |||
543 | nvgpu_info(g, "ldiv_slowdown_factor is %x\n", g->ldiv_slowdown_factor); | ||
544 | |||
545 | return count; | ||
546 | } | ||
547 | |||
548 | static ssize_t ldiv_slowdown_factor_read(struct device *dev, | ||
549 | struct device_attribute *attr, char *buf) | ||
550 | { | ||
551 | struct gk20a *g = get_gk20a(dev); | ||
552 | |||
553 | return snprintf(buf, PAGE_SIZE, "%d\n", g->ldiv_slowdown_factor); | ||
554 | } | ||
555 | |||
556 | static DEVICE_ATTR(ldiv_slowdown_factor, ROOTRW, | ||
557 | ldiv_slowdown_factor_read, ldiv_slowdown_factor_store); | ||
558 | |||
507 | static ssize_t mscg_enable_store(struct device *dev, | 559 | static ssize_t mscg_enable_store(struct device *dev, |
508 | struct device_attribute *attr, const char *buf, size_t count) | 560 | struct device_attribute *attr, const char *buf, size_t count) |
509 | { | 561 | { |
@@ -1114,6 +1166,7 @@ int nvgpu_create_sysfs(struct device *dev) | |||
1114 | error |= device_create_file(dev, &dev_attr_elpg_enable); | 1166 | error |= device_create_file(dev, &dev_attr_elpg_enable); |
1115 | error |= device_create_file(dev, &dev_attr_mscg_enable); | 1167 | error |= device_create_file(dev, &dev_attr_mscg_enable); |
1116 | error |= device_create_file(dev, &dev_attr_emc3d_ratio); | 1168 | error |= device_create_file(dev, &dev_attr_emc3d_ratio); |
1169 | error |= device_create_file(dev, &dev_attr_ldiv_slowdown_factor); | ||
1117 | #ifdef CONFIG_TEGRA_DVFS | 1170 | #ifdef CONFIG_TEGRA_DVFS |
1118 | error |= device_create_file(dev, &dev_attr_fmax_at_vmin_safe); | 1171 | error |= device_create_file(dev, &dev_attr_fmax_at_vmin_safe); |
1119 | #endif | 1172 | #endif |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c index ed4e6c20..c610c391 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_fw.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_fw.c | |||
@@ -39,7 +39,7 @@ | |||
39 | #define APP_VERSION_GV11B 23416738 | 39 | #define APP_VERSION_GV11B 23416738 |
40 | #define APP_VERSION_GV10X 23616379 | 40 | #define APP_VERSION_GV10X 23616379 |
41 | #define APP_VERSION_GP10X 24008084 | 41 | #define APP_VERSION_GP10X 24008084 |
42 | #define APP_VERSION_GP10B 20429989 | 42 | #define APP_VERSION_GP10B 23782727 |
43 | #define APP_VERSION_GM20B 20490253 | 43 | #define APP_VERSION_GM20B 20490253 |
44 | 44 | ||
45 | /* PMU version specific functions */ | 45 | /* PMU version specific functions */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index bf2e0dbb..476c1dd3 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1333,7 +1333,7 @@ struct gk20a { | |||
1333 | bool can_railgate; | 1333 | bool can_railgate; |
1334 | bool user_railgate_disabled; | 1334 | bool user_railgate_disabled; |
1335 | int railgate_delay; | 1335 | int railgate_delay; |
1336 | 1336 | u8 ldiv_slowdown_factor; | |
1337 | unsigned int aggressive_sync_destroy_thresh; | 1337 | unsigned int aggressive_sync_destroy_thresh; |
1338 | bool aggressive_sync_destroy; | 1338 | bool aggressive_sync_destroy; |
1339 | 1339 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index 49ad3920..c94d580a 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B PMU | 2 | * GP10B PMU |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -233,13 +233,15 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
233 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 233 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
234 | cmd.hdr.unit_id = PMU_UNIT_PG; | 234 | cmd.hdr.unit_id = PMU_UNIT_PG; |
235 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | 235 | cmd.hdr.size = PMU_CMD_HDR_SIZE + |
236 | sizeof(struct pmu_pg_cmd_gr_init_param); | 236 | sizeof(struct pmu_pg_cmd_gr_init_param_v2); |
237 | cmd.cmd.pg.gr_init_param.cmd_type = | 237 | cmd.cmd.pg.gr_init_param_v2.cmd_type = |
238 | PMU_PG_CMD_ID_PG_PARAM; | 238 | PMU_PG_CMD_ID_PG_PARAM; |
239 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | 239 | cmd.cmd.pg.gr_init_param_v2.sub_cmd_id = |
240 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | 240 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; |
241 | cmd.cmd.pg.gr_init_param.featuremask = | 241 | cmd.cmd.pg.gr_init_param_v2.featuremask = |
242 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; | 242 | NVGPU_PMU_GR_FEATURE_MASK_POWER_GATING; |
243 | cmd.cmd.pg.gr_init_param_v2.ldiv_slowdown_factor = | ||
244 | g->ldiv_slowdown_factor; | ||
243 | 245 | ||
244 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); | 246 | gp10b_dbg_pmu("cmd post PMU_PG_CMD_ID_PG_PARAM "); |
245 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 247 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h index 91656156..1ba9963c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuif_pg.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -122,6 +122,57 @@ enum { | |||
122 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, | 122 | PMU_PG_STAT_CMD_ALLOC_DMEM = 0, |
123 | }; | 123 | }; |
124 | 124 | ||
125 | enum { | ||
126 | SLOWDOWN_FACTOR_FPDIV_BY1 = 0, | ||
127 | SLOWDOWN_FACTOR_FPDIV_BY1P5, | ||
128 | SLOWDOWN_FACTOR_FPDIV_BY2, | ||
129 | SLOWDOWN_FACTOR_FPDIV_BY2P5, | ||
130 | SLOWDOWN_FACTOR_FPDIV_BY3, | ||
131 | SLOWDOWN_FACTOR_FPDIV_BY3P5, | ||
132 | SLOWDOWN_FACTOR_FPDIV_BY4, | ||
133 | SLOWDOWN_FACTOR_FPDIV_BY4P5, | ||
134 | SLOWDOWN_FACTOR_FPDIV_BY5, | ||
135 | SLOWDOWN_FACTOR_FPDIV_BY5P5, | ||
136 | SLOWDOWN_FACTOR_FPDIV_BY6, | ||
137 | SLOWDOWN_FACTOR_FPDIV_BY6P5, | ||
138 | SLOWDOWN_FACTOR_FPDIV_BY7, | ||
139 | SLOWDOWN_FACTOR_FPDIV_BY7P5, | ||
140 | SLOWDOWN_FACTOR_FPDIV_BY8, | ||
141 | SLOWDOWN_FACTOR_FPDIV_BY8P5, | ||
142 | SLOWDOWN_FACTOR_FPDIV_BY9, | ||
143 | SLOWDOWN_FACTOR_FPDIV_BY9P5, | ||
144 | SLOWDOWN_FACTOR_FPDIV_BY10, | ||
145 | SLOWDOWN_FACTOR_FPDIV_BY10P5, | ||
146 | SLOWDOWN_FACTOR_FPDIV_BY11, | ||
147 | SLOWDOWN_FACTOR_FPDIV_BY11P5, | ||
148 | SLOWDOWN_FACTOR_FPDIV_BY12, | ||
149 | SLOWDOWN_FACTOR_FPDIV_BY12P5, | ||
150 | SLOWDOWN_FACTOR_FPDIV_BY13, | ||
151 | SLOWDOWN_FACTOR_FPDIV_BY13P5, | ||
152 | SLOWDOWN_FACTOR_FPDIV_BY14, | ||
153 | SLOWDOWN_FACTOR_FPDIV_BY14P5, | ||
154 | SLOWDOWN_FACTOR_FPDIV_BY15, | ||
155 | SLOWDOWN_FACTOR_FPDIV_BY15P5, | ||
156 | SLOWDOWN_FACTOR_FPDIV_BY16, | ||
157 | SLOWDOWN_FACTOR_FPDIV_BY16P5, | ||
158 | SLOWDOWN_FACTOR_FPDIV_BY17 = 0x20, | ||
159 | SLOWDOWN_FACTOR_FPDIV_BY18 = 0x22, | ||
160 | SLOWDOWN_FACTOR_FPDIV_BY19 = 0x24, | ||
161 | SLOWDOWN_FACTOR_FPDIV_BY20 = 0x26, | ||
162 | SLOWDOWN_FACTOR_FPDIV_BY21 = 0x28, | ||
163 | SLOWDOWN_FACTOR_FPDIV_BY22 = 0x2a, | ||
164 | SLOWDOWN_FACTOR_FPDIV_BY23 = 0x2c, | ||
165 | SLOWDOWN_FACTOR_FPDIV_BY24 = 0x2e, | ||
166 | SLOWDOWN_FACTOR_FPDIV_BY25 = 0x30, | ||
167 | SLOWDOWN_FACTOR_FPDIV_BY26 = 0x32, | ||
168 | SLOWDOWN_FACTOR_FPDIV_BY27 = 0x34, | ||
169 | SLOWDOWN_FACTOR_FPDIV_BY28 = 0x36, | ||
170 | SLOWDOWN_FACTOR_FPDIV_BY29 = 0x38, | ||
171 | SLOWDOWN_FACTOR_FPDIV_BY30 = 0x3a, | ||
172 | SLOWDOWN_FACTOR_FPDIV_BY31 = 0x3c, | ||
173 | SLOWDOWN_FACTOR_FPDIV_BYMAX, | ||
174 | }; | ||
175 | |||
125 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 | 176 | #define PMU_PG_PARAM_CMD_GR_INIT_PARAM 0x0 |
126 | #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 | 177 | #define PMU_PG_PARAM_CMD_MS_INIT_PARAM 0x01 |
127 | #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 | 178 | #define PMU_PG_PARAM_CMD_MCLK_CHANGE 0x04 |
@@ -212,6 +263,13 @@ struct pmu_pg_cmd_gr_init_param { | |||
212 | u8 featuremask; | 263 | u8 featuremask; |
213 | }; | 264 | }; |
214 | 265 | ||
266 | struct pmu_pg_cmd_gr_init_param_v2 { | ||
267 | u8 cmd_type; | ||
268 | u16 sub_cmd_id; | ||
269 | u8 featuremask; | ||
270 | u8 ldiv_slowdown_factor; | ||
271 | }; | ||
272 | |||
215 | struct pmu_pg_cmd_gr_init_param_v1 { | 273 | struct pmu_pg_cmd_gr_init_param_v1 { |
216 | u8 cmd_type; | 274 | u8 cmd_type; |
217 | u16 sub_cmd_id; | 275 | u16 sub_cmd_id; |
@@ -277,6 +335,7 @@ struct pmu_pg_cmd { | |||
277 | struct pmu_pg_cmd_stat stat; | 335 | struct pmu_pg_cmd_stat stat; |
278 | struct pmu_pg_cmd_gr_init_param gr_init_param; | 336 | struct pmu_pg_cmd_gr_init_param gr_init_param; |
279 | struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1; | 337 | struct pmu_pg_cmd_gr_init_param_v1 gr_init_param_v1; |
338 | struct pmu_pg_cmd_gr_init_param_v2 gr_init_param_v2; | ||
280 | struct pmu_pg_cmd_ms_init_param ms_init_param; | 339 | struct pmu_pg_cmd_ms_init_param ms_init_param; |
281 | struct pmu_pg_cmd_mclk_change mclk_change; | 340 | struct pmu_pg_cmd_mclk_change mclk_change; |
282 | struct pmu_pg_cmd_post_init_param post_init; | 341 | struct pmu_pg_cmd_post_init_param post_init; |