diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 59 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | 8 |
2 files changed, 67 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index a86a9509..5425eaa0 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -1401,6 +1401,63 @@ static unsigned int gv11b_fifo_handle_pbdma_intr_0(struct gk20a *g, | |||
1401 | return rc_type; | 1401 | return rc_type; |
1402 | } | 1402 | } |
1403 | 1403 | ||
1404 | /* | ||
1405 | * Pbdma which encountered the ctxnotvalid interrupt will stall and | ||
1406 | * prevent the channel which was loaded at the time the interrupt fired | ||
1407 | * from being swapped out until the interrupt is cleared. | ||
1408 | * CTXNOTVALID pbdma interrupt indicates error conditions related | ||
1409 | * to the *_CTX_VALID fields for a channel. The following | ||
1410 | * conditions trigger the interrupt: | ||
1411 | * * CTX_VALID bit for the targeted engine is FALSE | ||
1412 | * * At channel start/resume, all preemptible eng have CTX_VALID FALSE but: | ||
1413 | * - CTX_RELOAD is set in CCSR_CHANNEL_STATUS, | ||
1414 | * - PBDMA_TARGET_SHOULD_SEND_HOST_TSG_EVENT is TRUE, or | ||
1415 | * - PBDMA_TARGET_NEEDS_HOST_TSG_EVENT is TRUE | ||
1416 | * The field is left NOT_PENDING and the interrupt is not raised if the PBDMA is | ||
1417 | * currently halted. This allows SW to unblock the PBDMA and recover. | ||
1418 | * SW may read METHOD0, CHANNEL_STATUS and TARGET to determine whether the | ||
1419 | * interrupt was due to an engine method, CTX_RELOAD, SHOULD_SEND_HOST_TSG_EVENT | ||
1420 | * or NEEDS_HOST_TSG_EVENT. If METHOD0 VALID is TRUE, lazy context creation | ||
1421 | * can be used or the TSG may be destroyed. | ||
1422 | * If METHOD0 VALID is FALSE, the error is likely a bug in SW, and the TSG | ||
1423 | * will have to be destroyed. | ||
1424 | */ | ||
1425 | |||
1426 | static unsigned int gv11b_fifo_handle_pbdma_intr_1(struct gk20a *g, | ||
1427 | u32 pbdma_id, u32 pbdma_intr_1, | ||
1428 | u32 *handled, u32 *error_notifier) | ||
1429 | { | ||
1430 | unsigned int rc_type = RC_TYPE_PBDMA_FAULT; | ||
1431 | u32 pbdma_intr_1_current = gk20a_readl(g, pbdma_intr_1_r(pbdma_id)); | ||
1432 | |||
1433 | /* minimize race with the gpu clearing the pending interrupt */ | ||
1434 | if (!(pbdma_intr_1_current & | ||
1435 | pbdma_intr_1_ctxnotvalid_pending_f())) | ||
1436 | pbdma_intr_1 &= ~pbdma_intr_1_ctxnotvalid_pending_f(); | ||
1437 | |||
1438 | if (pbdma_intr_1 == 0) | ||
1439 | return RC_TYPE_NO_RC; | ||
1440 | |||
1441 | if (pbdma_intr_1 & pbdma_intr_1_ctxnotvalid_pending_f()) { | ||
1442 | gk20a_dbg(gpu_dbg_intr, "ctxnotvalid intr on pbdma id %d", | ||
1443 | pbdma_id); | ||
1444 | nvgpu_err(g, "pbdma_intr_1(%d)= 0x%08x ", | ||
1445 | pbdma_id, pbdma_intr_1); | ||
1446 | *handled |= pbdma_intr_1_ctxnotvalid_pending_f(); | ||
1447 | } else{ | ||
1448 | /* | ||
1449 | * rest of the interrupts in _intr_1 are "host copy engine" | ||
1450 | * related, which is not supported. For now just make them | ||
1451 | * channel fatal. | ||
1452 | */ | ||
1453 | nvgpu_err(g, "hce err: pbdma_intr_1(%d):0x%08x", | ||
1454 | pbdma_id, pbdma_intr_1); | ||
1455 | *handled |= pbdma_intr_1; | ||
1456 | } | ||
1457 | |||
1458 | return rc_type; | ||
1459 | } | ||
1460 | |||
1404 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 1461 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
1405 | static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | 1462 | static int gv11b_fifo_alloc_syncpt_buf(struct channel_gk20a *c, |
1406 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) | 1463 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf) |
@@ -1554,6 +1611,8 @@ void gv11b_init_fifo(struct gpu_ops *gops) | |||
1554 | gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; | 1611 | gops->fifo.handle_ctxsw_timeout = gv11b_fifo_handle_ctxsw_timeout; |
1555 | gops->fifo.handle_pbdma_intr_0 = | 1612 | gops->fifo.handle_pbdma_intr_0 = |
1556 | gv11b_fifo_handle_pbdma_intr_0; | 1613 | gv11b_fifo_handle_pbdma_intr_0; |
1614 | gops->fifo.handle_pbdma_intr_1 = | ||
1615 | gv11b_fifo_handle_pbdma_intr_1; | ||
1557 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | 1616 | #ifdef CONFIG_TEGRA_GK20A_NVHOST |
1558 | gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; | 1617 | gops->fifo.alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf; |
1559 | gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; | 1618 | gops->fifo.free_syncpt_buf = gv11b_fifo_free_syncpt_buf; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h index ed63cebc..abdbc17d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_pbdma_gv11b.h | |||
@@ -502,6 +502,14 @@ static inline u32 pbdma_intr_1_r(u32 i) | |||
502 | { | 502 | { |
503 | return 0x00040148 + i*8192; | 503 | return 0x00040148 + i*8192; |
504 | } | 504 | } |
505 | static inline u32 pbdma_intr_1_ctxnotvalid_m(void) | ||
506 | { | ||
507 | return 0x1 << 31; | ||
508 | } | ||
509 | static inline u32 pbdma_intr_1_ctxnotvalid_pending_f(void) | ||
510 | { | ||
511 | return 0x80000000; | ||
512 | } | ||
505 | static inline u32 pbdma_intr_en_0_r(u32 i) | 513 | static inline u32 pbdma_intr_en_0_r(u32 i) |
506 | { | 514 | { |
507 | return 0x0004010c + i*8192; | 515 | return 0x0004010c + i*8192; |