diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 7 |
2 files changed, 8 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e3dad962..d781034c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -368,6 +368,7 @@ struct gpu_ops { | |||
368 | bool (*is_debug_mode_enabled)(struct gk20a *g); | 368 | bool (*is_debug_mode_enabled)(struct gk20a *g); |
369 | void (*set_debug_mode)(struct gk20a *g, bool enable); | 369 | void (*set_debug_mode)(struct gk20a *g, bool enable); |
370 | void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); | 370 | void (*tlb_invalidate)(struct gk20a *g, struct mem_desc *pdb); |
371 | void (*hub_isr)(struct gk20a *g); | ||
371 | } fb; | 372 | } fb; |
372 | struct { | 373 | struct { |
373 | void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); | 374 | void (*slcg_bus_load_gating_prod)(struct gk20a *g, bool prod); |
@@ -758,6 +759,7 @@ struct gpu_ops { | |||
758 | irqreturn_t (*isr_thread_stall)(struct gk20a *g); | 759 | irqreturn_t (*isr_thread_stall)(struct gk20a *g); |
759 | void (*isr_thread_nonstall)(struct gk20a *g, u32 intr); | 760 | void (*isr_thread_nonstall)(struct gk20a *g, u32 intr); |
760 | void (*isr_nonstall_cb)(struct work_struct *work); | 761 | void (*isr_nonstall_cb)(struct work_struct *work); |
762 | bool (*is_intr_hub_pending)(struct gk20a *g, u32 mc_intr); | ||
761 | u32 intr_mask_restore[4]; | 763 | u32 intr_mask_restore[4]; |
762 | void (*enable)(struct gk20a *g, u32 units); | 764 | void (*enable)(struct gk20a *g, u32 units); |
763 | void (*disable)(struct gk20a *g, u32 units); | 765 | void (*disable)(struct gk20a *g, u32 units); |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 4b0cbc1c..4a8dc4c1 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -131,7 +131,7 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
131 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); | 131 | mc_intr_0 = gk20a_readl(g, mc_intr_r(0)); |
132 | hw_irq_count = atomic_read(&g->hw_irq_stall_count); | 132 | hw_irq_count = atomic_read(&g->hw_irq_stall_count); |
133 | 133 | ||
134 | gk20a_dbg(gpu_dbg_intr, "stall intr %08x\n", mc_intr_0); | 134 | gk20a_dbg(gpu_dbg_intr, "stall intr 0x%08x\n", mc_intr_0); |
135 | 135 | ||
136 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { | 136 | for (engine_id_idx = 0; engine_id_idx < g->fifo.num_engines; engine_id_idx++) { |
137 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; | 137 | active_engine_id = g->fifo.active_engines_list[engine_id_idx]; |
@@ -153,6 +153,9 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
153 | } | 153 | } |
154 | } | 154 | } |
155 | } | 155 | } |
156 | if (g->ops.mc.is_intr_hub_pending && | ||
157 | g->ops.mc.is_intr_hub_pending(g, mc_intr_0)) | ||
158 | g->ops.fb.hub_isr(g); | ||
156 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) | 159 | if (mc_intr_0 & mc_intr_pfifo_pending_f()) |
157 | gk20a_fifo_isr(g); | 160 | gk20a_fifo_isr(g); |
158 | if (mc_intr_0 & mc_intr_pmu_pending_f()) | 161 | if (mc_intr_0 & mc_intr_pmu_pending_f()) |
@@ -167,6 +170,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
167 | /* sync handled irq counter before re-enabling interrupts */ | 170 | /* sync handled irq counter before re-enabling interrupts */ |
168 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); | 171 | atomic_set(&g->sw_irq_stall_last_handled, hw_irq_count); |
169 | 172 | ||
173 | gk20a_dbg(gpu_dbg_intr, "stall intr done 0x%08x\n", mc_intr_0); | ||
174 | |||
170 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), | 175 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
171 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); | 176 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
172 | 177 | ||