2 files changed, 7 insertions, 11 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 01537042..fc98b5ca 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -511,23 +511,18 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 
 static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
 {
-#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
-        tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0);
-        tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0);
-#else
         tegra_fuse_control_write(0x1, FUSE_FUSEBYPASS_0);
         tegra_fuse_control_write(0x0, FUSE_WRITE_ACCESS_SW_0);
-#endif
 
         if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) {
-                tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
+                tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC1_DISABLE_0);
         } else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) {
-                tegra_fuse_writel(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                tegra_fuse_control_write(0x1, FUSE_OPT_GPU_TPC0_DISABLE_0);
+                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
         } else {
-                tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
-                tegra_fuse_writel(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
+                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC0_DISABLE_0);
+                tegra_fuse_control_write(0x0, FUSE_OPT_GPU_TPC1_DISABLE_0);
         }
 }
 
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 84eb3862..a1aef80b 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -29,6 +29,7 @@ enum {
 };
 
 #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0)
+#define tegra_fuse_control_write tegra_fuse_writel
 #define FUSE_FUSEBYPASS_0                               0x24
 #define FUSE_WRITE_ACCESS_SW_0                          0x30
 #define FUSE_OPT_GPU_TPC0_DISABLE_0                     0x30C