diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 4 |
9 files changed, 55 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d9a8396f..a1c9c2bd 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * GK20A Graphics | 4 | * GK20A Graphics |
5 | * | 5 | * |
@@ -437,6 +437,8 @@ struct gpu_ops { | |||
437 | unsigned long (*get_max_gfxp_wfi_timeout_count) | 437 | unsigned long (*get_max_gfxp_wfi_timeout_count) |
438 | (struct gk20a *g); | 438 | (struct gk20a *g); |
439 | void (*ecc_init_scrub_reg)(struct gk20a *g); | 439 | void (*ecc_init_scrub_reg)(struct gk20a *g); |
440 | u32 (*get_gpcs_swdx_dss_zbc_c_format_reg)(struct gk20a *g); | ||
441 | u32 (*get_gpcs_swdx_dss_zbc_z_format_reg)(struct gk20a *g); | ||
440 | } gr; | 442 | } gr; |
441 | struct { | 443 | struct { |
442 | void (*init_hw)(struct gk20a *g); | 444 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 9052b4b2..dc3b7868 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP106 HAL interface | 2 | * GP106 HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -281,6 +281,10 @@ static const struct gpu_ops gp106_ops = { | |||
281 | .detect_sm_arch = gr_gm20b_detect_sm_arch, | 281 | .detect_sm_arch = gr_gm20b_detect_sm_arch, |
282 | .add_zbc_color = gr_gp10b_add_zbc_color, | 282 | .add_zbc_color = gr_gp10b_add_zbc_color, |
283 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 283 | .add_zbc_depth = gr_gp10b_add_zbc_depth, |
284 | .get_gpcs_swdx_dss_zbc_c_format_reg = | ||
285 | gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg, | ||
286 | .get_gpcs_swdx_dss_zbc_z_format_reg = | ||
287 | gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg, | ||
284 | .zbc_set_table = gk20a_gr_zbc_set_table, | 288 | .zbc_set_table = gk20a_gr_zbc_set_table, |
285 | .zbc_query_table = gr_gk20a_query_zbc, | 289 | .zbc_query_table = gr_gk20a_query_zbc, |
286 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 290 | .pmu_save_zbc = gk20a_pmu_save_zbc, |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 9a7f4f97..68d18aa1 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -507,11 +507,18 @@ void gr_gp10b_commit_global_pagepool(struct gk20a *g, | |||
507 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); | 507 | gr_gpcs_gcc_pagepool_total_pages_f(size), patch); |
508 | } | 508 | } |
509 | 509 | ||
510 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) | ||
511 | { | ||
512 | return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); | ||
513 | } | ||
514 | |||
510 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 515 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
511 | struct zbc_entry *color_val, u32 index) | 516 | struct zbc_entry *color_val, u32 index) |
512 | { | 517 | { |
513 | u32 i; | 518 | u32 i; |
514 | u32 zbc_c; | 519 | u32 zbc_c; |
520 | u32 zbc_c_format_reg = | ||
521 | g->ops.gr.get_gpcs_swdx_dss_zbc_c_format_reg(g); | ||
515 | 522 | ||
516 | /* update l2 table */ | 523 | /* update l2 table */ |
517 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | 524 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); |
@@ -554,18 +561,25 @@ int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
554 | color_val->color_ds[2]); | 561 | color_val->color_ds[2]); |
555 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), | 562 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_color_a_r(index), |
556 | color_val->color_ds[3]); | 563 | color_val->color_ds[3]); |
557 | zbc_c = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3)); | 564 | zbc_c = gk20a_readl(g, zbc_c_format_reg + (index & ~3)); |
558 | zbc_c &= ~(0x7f << ((index % 4) * 7)); | 565 | zbc_c &= ~(0x7f << ((index % 4) * 7)); |
559 | zbc_c |= color_val->format << ((index % 4) * 7); | 566 | zbc_c |= color_val->format << ((index % 4) * 7); |
560 | gk20a_writel_check(g, gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r() + (index & ~3), zbc_c); | 567 | gk20a_writel_check(g, zbc_c_format_reg + (index & ~3), zbc_c); |
561 | 568 | ||
562 | return 0; | 569 | return 0; |
563 | } | 570 | } |
564 | 571 | ||
572 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) | ||
573 | { | ||
574 | return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); | ||
575 | } | ||
576 | |||
565 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 577 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
566 | struct zbc_entry *depth_val, u32 index) | 578 | struct zbc_entry *depth_val, u32 index) |
567 | { | 579 | { |
568 | u32 zbc_z; | 580 | u32 zbc_z; |
581 | u32 zbc_z_format_reg = | ||
582 | g->ops.gr.get_gpcs_swdx_dss_zbc_z_format_reg(g); | ||
569 | 583 | ||
570 | /* update l2 table */ | 584 | /* update l2 table */ |
571 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | 585 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); |
@@ -592,10 +606,10 @@ int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
592 | gr->zbc_dep_tbl[index].ref_cnt++; | 606 | gr->zbc_dep_tbl[index].ref_cnt++; |
593 | 607 | ||
594 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); | 608 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_r(index), depth_val->depth); |
595 | zbc_z = gk20a_readl(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3)); | 609 | zbc_z = gk20a_readl(g, zbc_z_format_reg + (index & ~3)); |
596 | zbc_z &= ~(0x7f << (index % 4) * 7); | 610 | zbc_z &= ~(0x7f << (index % 4) * 7); |
597 | zbc_z |= depth_val->format << (index % 4) * 7; | 611 | zbc_z |= depth_val->format << (index % 4) * 7; |
598 | gk20a_writel(g, gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r() + (index & ~3), zbc_z); | 612 | gk20a_writel(g, zbc_z_format_reg + (index & ~3), zbc_z); |
599 | 613 | ||
600 | return 0; | 614 | return 0; |
601 | } | 615 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h index 3b0f0f2e..1d39a38b 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B GPU GR | 2 | * GP10B GPU GR |
3 | * | 3 | * |
4 | * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2015-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -77,6 +77,8 @@ int gr_gp10b_commit_global_cb_manager(struct gk20a *g, | |||
77 | void gr_gp10b_commit_global_pagepool(struct gk20a *g, | 77 | void gr_gp10b_commit_global_pagepool(struct gk20a *g, |
78 | struct channel_ctx_gk20a *ch_ctx, | 78 | struct channel_ctx_gk20a *ch_ctx, |
79 | u64 addr, u32 size, bool patch); | 79 | u64 addr, u32 size, bool patch); |
80 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); | ||
81 | u32 gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); | ||
80 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 82 | int gr_gp10b_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
81 | struct zbc_entry *color_val, u32 index); | 83 | struct zbc_entry *color_val, u32 index); |
82 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 84 | int gr_gp10b_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 5e8e7acc..cfba7d65 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B Tegra HAL interface | 2 | * GP10B Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -245,6 +245,10 @@ static const struct gpu_ops gp10b_ops = { | |||
245 | .detect_sm_arch = gr_gm20b_detect_sm_arch, | 245 | .detect_sm_arch = gr_gm20b_detect_sm_arch, |
246 | .add_zbc_color = gr_gp10b_add_zbc_color, | 246 | .add_zbc_color = gr_gp10b_add_zbc_color, |
247 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 247 | .add_zbc_depth = gr_gp10b_add_zbc_depth, |
248 | .get_gpcs_swdx_dss_zbc_c_format_reg = | ||
249 | gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg, | ||
250 | .get_gpcs_swdx_dss_zbc_z_format_reg = | ||
251 | gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg, | ||
248 | .zbc_set_table = gk20a_gr_zbc_set_table, | 252 | .zbc_set_table = gk20a_gr_zbc_set_table, |
249 | .zbc_query_table = gr_gk20a_query_zbc, | 253 | .zbc_query_table = gr_gk20a_query_zbc, |
250 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 254 | .pmu_save_zbc = gk20a_pmu_save_zbc, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9c847a55..e935b2e5 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GV100 Tegra HAL interface | 2 | * GV100 Tegra HAL interface |
3 | * | 3 | * |
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2017-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -314,6 +314,10 @@ static const struct gpu_ops gv100_ops = { | |||
314 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | 314 | .detect_sm_arch = gr_gv11b_detect_sm_arch, |
315 | .add_zbc_color = gr_gp10b_add_zbc_color, | 315 | .add_zbc_color = gr_gp10b_add_zbc_color, |
316 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 316 | .add_zbc_depth = gr_gp10b_add_zbc_depth, |
317 | .get_gpcs_swdx_dss_zbc_c_format_reg = | ||
318 | gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, | ||
319 | .get_gpcs_swdx_dss_zbc_z_format_reg = | ||
320 | gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, | ||
317 | .zbc_set_table = gk20a_gr_zbc_set_table, | 321 | .zbc_set_table = gk20a_gr_zbc_set_table, |
318 | .zbc_query_table = gr_gk20a_query_zbc, | 322 | .zbc_query_table = gr_gk20a_query_zbc, |
319 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 323 | .pmu_save_zbc = gk20a_pmu_save_zbc, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index f369e12e..baad5e47 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -4152,3 +4152,13 @@ void gr_gv11b_ecc_init_scrub_reg(struct gk20a *g) | |||
4152 | nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); | 4152 | nvgpu_warn(g, "ECC SCRUB SM ICACHE Failed"); |
4153 | 4153 | ||
4154 | } | 4154 | } |
4155 | |||
4156 | u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g) | ||
4157 | { | ||
4158 | return gr_gpcs_swdx_dss_zbc_c_01_to_04_format_r(); | ||
4159 | } | ||
4160 | |||
4161 | u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g) | ||
4162 | { | ||
4163 | return gr_gpcs_swdx_dss_zbc_z_01_to_04_format_r(); | ||
4164 | } | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 17e5e9e3..b69e69bd 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -102,6 +102,8 @@ int gr_gv11b_handle_gpc_gpcmmu_exception(struct gk20a *g, u32 gpc, | |||
102 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, | 102 | int gr_gv11b_handle_gpc_gpccs_exception(struct gk20a *g, u32 gpc, |
103 | u32 gpc_exception); | 103 | u32 gpc_exception); |
104 | void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); | 104 | void gr_gv11b_enable_gpc_exceptions(struct gk20a *g); |
105 | u32 gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg(struct gk20a *g); | ||
106 | u32 gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg(struct gk20a *g); | ||
105 | int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | 107 | int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, |
106 | bool *post_event); | 108 | bool *post_event); |
107 | int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, | 109 | int gr_gv11b_zbc_s_query_table(struct gk20a *g, struct gr_gk20a *gr, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9156d9b8..f19832b9 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -281,6 +281,10 @@ static const struct gpu_ops gv11b_ops = { | |||
281 | .detect_sm_arch = gr_gv11b_detect_sm_arch, | 281 | .detect_sm_arch = gr_gv11b_detect_sm_arch, |
282 | .add_zbc_color = gr_gp10b_add_zbc_color, | 282 | .add_zbc_color = gr_gp10b_add_zbc_color, |
283 | .add_zbc_depth = gr_gp10b_add_zbc_depth, | 283 | .add_zbc_depth = gr_gp10b_add_zbc_depth, |
284 | .get_gpcs_swdx_dss_zbc_c_format_reg = | ||
285 | gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg, | ||
286 | .get_gpcs_swdx_dss_zbc_z_format_reg = | ||
287 | gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg, | ||
284 | .zbc_set_table = gk20a_gr_zbc_set_table, | 288 | .zbc_set_table = gk20a_gr_zbc_set_table, |
285 | .zbc_query_table = gr_gk20a_query_zbc, | 289 | .zbc_query_table = gr_gk20a_query_zbc, |
286 | .pmu_save_zbc = gk20a_pmu_save_zbc, | 290 | .pmu_save_zbc = gk20a_pmu_save_zbc, |