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-rw-r--r--drivers/gpu/nvgpu/vgpu/fifo_vgpu.c37
1 files changed, 33 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index 3e89e81f..dad9464a 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -624,13 +624,42 @@ static int vgpu_channel_set_timeslice(struct channel_gk20a *ch, u32 timeslice)
624 624
625static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose) 625static int vgpu_fifo_force_reset_ch(struct channel_gk20a *ch, bool verbose)
626{ 626{
627 struct tsg_gk20a *tsg = NULL;
628 struct channel_gk20a *ch_tsg = NULL;
629 struct gk20a *g = ch->g;
630 struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev);
631 struct tegra_vgpu_cmd_msg msg = {0};
632 struct tegra_vgpu_channel_config_params *p =
633 &msg.params.channel_config;
634 int err;
635
627 gk20a_dbg_fn(""); 636 gk20a_dbg_fn("");
628 637
629 if (verbose) 638 if (gk20a_is_channel_marked_as_tsg(ch)) {
630 gk20a_warn(dev_from_gk20a(ch->g), 639 tsg = &g->fifo.tsg[ch->tsgid];
631 "channel force reset is not supported"); 640
641 mutex_lock(&tsg->ch_list_lock);
642
643 list_for_each_entry(ch_tsg, &tsg->ch_list, ch_entry) {
644 if (gk20a_channel_get(ch_tsg)) {
645 gk20a_set_error_notifier(ch_tsg,
646 NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
647 gk20a_channel_put(ch_tsg);
648 }
649 }
650
651 mutex_unlock(&tsg->ch_list_lock);
652 } else {
653 gk20a_set_error_notifier(ch,
654 NVGPU_CHANNEL_RESETCHANNEL_VERIF_ERROR);
655 }
632 656
633 return -ENOSYS; 657 msg.cmd = TEGRA_VGPU_CMD_CHANNEL_FORCE_RESET;
658 msg.handle = platform->virt_handle;
659 p->handle = ch->virt_ctx;
660 err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg));
661 WARN_ON(err || msg.ret);
662 return err ? err : msg.ret;
634} 663}
635 664
636static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, 665static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g,