diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 74 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 2 |
5 files changed, 15 insertions, 78 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index e43e58a0..3542a597 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -782,6 +782,14 @@ static inline u32 gk20a_readl(struct gk20a *g, u32 r) | |||
782 | gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); | 782 | gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); |
783 | return v; | 783 | return v; |
784 | } | 784 | } |
785 | static inline void gk20a_writel_check(struct gk20a *g, u32 r, u32 v) | ||
786 | { | ||
787 | gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v); | ||
788 | wmb(); | ||
789 | do { | ||
790 | writel_relaxed(v, g->regs + r); | ||
791 | } while (readl(g->regs + r) != v); | ||
792 | } | ||
785 | 793 | ||
786 | static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v) | 794 | static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v) |
787 | { | 795 | { |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 0cb18665..090f95a5 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3456,42 +3456,6 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
3456 | return 0; | 3456 | return 0; |
3457 | } | 3457 | } |
3458 | 3458 | ||
3459 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | ||
3460 | { | ||
3461 | struct fifo_gk20a *f = &g->fifo; | ||
3462 | struct fifo_engine_info_gk20a *gr_info = | ||
3463 | f->engine_info + ENGINE_GR_GK20A; | ||
3464 | unsigned long end_jiffies = jiffies + | ||
3465 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3466 | u32 ret; | ||
3467 | |||
3468 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3469 | if (ret) { | ||
3470 | gk20a_err(dev_from_gk20a(g), | ||
3471 | "failed to disable gr engine activity\n"); | ||
3472 | return; | ||
3473 | } | ||
3474 | |||
3475 | ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3476 | if (ret) { | ||
3477 | gk20a_err(dev_from_gk20a(g), | ||
3478 | "failed to idle graphics\n"); | ||
3479 | goto clean_up; | ||
3480 | } | ||
3481 | |||
3482 | /* update zbc */ | ||
3483 | gk20a_pmu_save_zbc(g, entries); | ||
3484 | |||
3485 | clean_up: | ||
3486 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3487 | if (ret) { | ||
3488 | gk20a_err(dev_from_gk20a(g), | ||
3489 | "failed to enable gr engine activity\n"); | ||
3490 | } | ||
3491 | |||
3492 | return; | ||
3493 | } | ||
3494 | |||
3495 | int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | 3459 | int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, |
3496 | struct zbc_entry *zbc_val) | 3460 | struct zbc_entry *zbc_val) |
3497 | { | 3461 | { |
@@ -3584,7 +3548,7 @@ int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | |||
3584 | /* update zbc for elpg only when new entry is added */ | 3548 | /* update zbc for elpg only when new entry is added */ |
3585 | entries = max(gr->max_used_color_index, | 3549 | entries = max(gr->max_used_color_index, |
3586 | gr->max_used_depth_index); | 3550 | gr->max_used_depth_index); |
3587 | gr_gk20a_pmu_save_zbc(g, entries); | 3551 | gk20a_pmu_save_zbc(g, entries); |
3588 | } | 3552 | } |
3589 | 3553 | ||
3590 | err_mutex: | 3554 | err_mutex: |
@@ -3739,47 +3703,13 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3739 | return 0; | 3703 | return 0; |
3740 | } | 3704 | } |
3741 | 3705 | ||
3742 | static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | ||
3743 | struct zbc_entry *zbc_val) | ||
3744 | { | ||
3745 | struct fifo_gk20a *f = &g->fifo; | ||
3746 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3747 | unsigned long end_jiffies; | ||
3748 | int ret; | ||
3749 | |||
3750 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3751 | if (ret) { | ||
3752 | gk20a_err(dev_from_gk20a(g), | ||
3753 | "failed to disable gr engine activity\n"); | ||
3754 | return ret; | ||
3755 | } | ||
3756 | |||
3757 | end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3758 | ret = g->ops.gr.wait_empty(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3759 | if (ret) { | ||
3760 | gk20a_err(dev_from_gk20a(g), | ||
3761 | "failed to idle graphics\n"); | ||
3762 | goto clean_up; | ||
3763 | } | ||
3764 | |||
3765 | ret = gr_gk20a_add_zbc(g, gr, zbc_val); | ||
3766 | |||
3767 | clean_up: | ||
3768 | if (gk20a_fifo_enable_engine_activity(g, gr_info)) { | ||
3769 | gk20a_err(dev_from_gk20a(g), | ||
3770 | "failed to enable gr engine activity\n"); | ||
3771 | } | ||
3772 | |||
3773 | return ret; | ||
3774 | } | ||
3775 | |||
3776 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | 3706 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, |
3777 | struct zbc_entry *zbc_val) | 3707 | struct zbc_entry *zbc_val) |
3778 | { | 3708 | { |
3779 | gk20a_dbg_fn(""); | 3709 | gk20a_dbg_fn(""); |
3780 | 3710 | ||
3781 | return gr_gk20a_elpg_protected_call(g, | 3711 | return gr_gk20a_elpg_protected_call(g, |
3782 | _gk20a_gr_zbc_set_table(g, gr, zbc_val)); | 3712 | gr_gk20a_add_zbc(g, gr, zbc_val)); |
3783 | } | 3713 | } |
3784 | 3714 | ||
3785 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | 3715 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 6444a22d..55c5ceb7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -429,8 +429,6 @@ int gr_gk20a_fecs_set_reglist_virtual_addr(struct gk20a *g, u64 pmu_va); | |||
429 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); | 429 | void gr_gk20a_init_elcg_mode(struct gk20a *g, u32 mode, u32 engine); |
430 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); | 430 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine); |
431 | 431 | ||
432 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries); | ||
433 | |||
434 | /* sm */ | 432 | /* sm */ |
435 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); | 433 | bool gk20a_gr_sm_debugger_attached(struct gk20a *g); |
436 | 434 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c index 6fbd0c2d..1c18418c 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_common.c | |||
@@ -52,9 +52,10 @@ static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, | |||
52 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 52 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
53 | 53 | ||
54 | for (i = 0; | 54 | for (i = 0; |
55 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) | 55 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { |
56 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | 56 | gk20a_writel_check(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), |
57 | color_val->color_l2[i]); | 57 | color_val->color_l2[i]); |
58 | } | ||
58 | } | 59 | } |
59 | 60 | ||
60 | /* | 61 | /* |
@@ -69,7 +70,7 @@ static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, | |||
69 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | 70 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), |
70 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | 71 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); |
71 | 72 | ||
72 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | 73 | gk20a_writel_check(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), |
73 | depth_val->depth); | 74 | depth_val->depth); |
74 | } | 75 | } |
75 | 76 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 744a852e..0ff3838a 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2737,7 +2737,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
2737 | 2737 | ||
2738 | pmu->zbc_ready = true; | 2738 | pmu->zbc_ready = true; |
2739 | /* Save zbc table after PMU is initialized. */ | 2739 | /* Save zbc table after PMU is initialized. */ |
2740 | gr_gk20a_pmu_save_zbc(g, 0xf); | 2740 | gk20a_pmu_save_zbc(g, 0xf); |
2741 | 2741 | ||
2742 | if (g->elpg_enabled) { | 2742 | if (g->elpg_enabled) { |
2743 | /* Init reg with prod values*/ | 2743 | /* Init reg with prod values*/ |