diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlvolt.h | 60 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 194 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_dev.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_dev.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_pmu.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_policy.c | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/volt/volt_rail.h | 4 |
9 files changed, 152 insertions, 152 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h index 9e4402a5..8f57e880 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlboardobj.h | |||
@@ -27,20 +27,20 @@ struct ctrl_boardobj { | |||
27 | u8 type; | 27 | u8 type; |
28 | }; | 28 | }; |
29 | 29 | ||
30 | #define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00 | 30 | #define CTRL_BOARDOBJGRP_TYPE_INVALID 0x00U |
31 | #define CTRL_BOARDOBJGRP_TYPE_E32 0x01 | 31 | #define CTRL_BOARDOBJGRP_TYPE_E32 0x01U |
32 | #define CTRL_BOARDOBJGRP_TYPE_E255 0x02 | 32 | #define CTRL_BOARDOBJGRP_TYPE_E255 0x02U |
33 | 33 | ||
34 | #define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32 | 34 | #define CTRL_BOARDOBJGRP_E32_MAX_OBJECTS 32U |
35 | 35 | ||
36 | #define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255 | 36 | #define CTRL_BOARDOBJGRP_E255_MAX_OBJECTS 255U |
37 | 37 | ||
38 | #define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ | 38 | #define CTRL_BOARDOBJ_MAX_BOARD_OBJECTS \ |
39 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS | 39 | CTRL_BOARDOBJGRP_E32_MAX_OBJECTS |
40 | 40 | ||
41 | #define CTRL_BOARDOBJ_IDX_INVALID 255 | 41 | #define CTRL_BOARDOBJ_IDX_INVALID 255U |
42 | 42 | ||
43 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32 | 43 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE 32U |
44 | 44 | ||
45 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ | 45 | #define CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX(_bit) \ |
46 | ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) | 46 | ((_bit) / CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) |
@@ -49,10 +49,10 @@ struct ctrl_boardobj { | |||
49 | ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) | 49 | ((_bit) % CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_BIT_SIZE) |
50 | 50 | ||
51 | #define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ | 51 | #define CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) \ |
52 | (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1) + 1) | 52 | (CTRL_BOARDOBJGRP_MASK_MASK_ELEMENT_INDEX((_bits) - 1U) + 1U) |
53 | 53 | ||
54 | 54 | ||
55 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1 | 55 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE 1U |
56 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ | 56 | #define CTRL_BOARDOBJGRP_MASK_ARRAY_EXTENSION_SIZE(_bits) \ |
57 | (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ | 57 | (CTRL_BOARDOBJGRP_MASK_DATA_SIZE(_bits) - \ |
58 | CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) | 58 | CTRL_BOARDOBJGRP_MASK_ARRAY_START_SIZE) |
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h index ea06dbc4..84994eb6 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlvolt.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlvolt.h | |||
@@ -30,25 +30,25 @@ | |||
30 | #include "ctrlperf.h" | 30 | #include "ctrlperf.h" |
31 | #include "ctrlboardobj.h" | 31 | #include "ctrlboardobj.h" |
32 | 32 | ||
33 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 | 33 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U |
34 | #define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8) | 34 | #define CTRL_VOLT_VOLT_DEV_VID_VSEL_MAX_ENTRIES (8U) |
35 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | 35 | #define CTRL_VOLT_DOMAIN_INVALID 0x00U |
36 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | 36 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01U |
37 | #define CLK_PROG_VFE_ENTRY_LOGIC 0x00 | 37 | #define CLK_PROG_VFE_ENTRY_LOGIC 0x00U |
38 | #define CLK_PROG_VFE_ENTRY_SRAM 0x01 | 38 | #define CLK_PROG_VFE_ENTRY_SRAM 0x01U |
39 | 39 | ||
40 | /* | 40 | /* |
41 | * Macros for Voltage Domain HAL. | 41 | * Macros for Voltage Domain HAL. |
42 | */ | 42 | */ |
43 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00 | 43 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL 0x00U |
44 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01 | 44 | #define CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL 0x01U |
45 | 45 | ||
46 | /* | 46 | /* |
47 | * Macros for Voltage Domains. | 47 | * Macros for Voltage Domains. |
48 | */ | 48 | */ |
49 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | 49 | #define CTRL_VOLT_DOMAIN_INVALID 0x00U |
50 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | 50 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01U |
51 | #define CTRL_VOLT_DOMAIN_SRAM 0x02 | 51 | #define CTRL_VOLT_DOMAIN_SRAM 0x02U |
52 | 52 | ||
53 | /*! | 53 | /*! |
54 | * Special value corresponding to an invalid Voltage Rail Index. | 54 | * Special value corresponding to an invalid Voltage Rail Index. |
@@ -79,43 +79,43 @@ enum nv_pmu_pmgr_pwm_source { | |||
79 | /*! | 79 | /*! |
80 | * Macros for Voltage Device Types. | 80 | * Macros for Voltage Device Types. |
81 | */ | 81 | */ |
82 | #define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00 | 82 | #define CTRL_VOLT_DEVICE_TYPE_INVALID 0x00U |
83 | #define CTRL_VOLT_DEVICE_TYPE_PWM 0x03 | 83 | #define CTRL_VOLT_DEVICE_TYPE_PWM 0x03U |
84 | 84 | ||
85 | /* | 85 | /* |
86 | * Macros for Volt Device Operation types. | 86 | * Macros for Volt Device Operation types. |
87 | */ | 87 | */ |
88 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00 | 88 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID 0x00U |
89 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01 | 89 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT 0x01U |
90 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02 | 90 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE 0x02U |
91 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03 | 91 | #define CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE 0x03U |
92 | #define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04 | 92 | #define CTRL_VOLT_VOLT_DEVICE_OPERATION_TYPE_IPC_VMIN 0x04U |
93 | 93 | ||
94 | /*! | 94 | /*! |
95 | * Macros for Voltage Domains. | 95 | * Macros for Voltage Domains. |
96 | */ | 96 | */ |
97 | #define CTRL_VOLT_DOMAIN_INVALID 0x00 | 97 | #define CTRL_VOLT_DOMAIN_INVALID 0x00U |
98 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01 | 98 | #define CTRL_VOLT_DOMAIN_LOGIC 0x01U |
99 | #define CTRL_VOLT_DOMAIN_SRAM 0x02 | 99 | #define CTRL_VOLT_DOMAIN_SRAM 0x02U |
100 | 100 | ||
101 | /*! | 101 | /*! |
102 | * Macros for Volt Policy types. | 102 | * Macros for Volt Policy types. |
103 | * | 103 | * |
104 | * Virtual VOLT_POLICY types are indexed starting from 0xFF. | 104 | * Virtual VOLT_POLICY types are indexed starting from 0xFF. |
105 | */ | 105 | */ |
106 | #define CTRL_VOLT_POLICY_TYPE_INVALID 0x00 | 106 | #define CTRL_VOLT_POLICY_TYPE_INVALID 0x00U |
107 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01 | 107 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL 0x01U |
108 | #define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02 | 108 | #define CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP 0x02U |
109 | #define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03 | 109 | #define CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP 0x03U |
110 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 | 110 | #define CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U |
111 | #define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFE | 111 | #define CTRL_VOLT_POLICY_TYPE_SPLIT_RAIL 0xFEU |
112 | #define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFF | 112 | #define CTRL_VOLT_POLICY_TYPE_UNKNOWN 0xFFU |
113 | 113 | ||
114 | /*! | 114 | /*! |
115 | * Macros for Volt Policy Client types. | 115 | * Macros for Volt Policy Client types. |
116 | */ | 116 | */ |
117 | #define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00 | 117 | #define CTRL_VOLT_POLICY_CLIENT_INVALID 0x00U |
118 | #define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01 | 118 | #define CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ 0x01U |
119 | 119 | ||
120 | struct ctrl_volt_volt_rail_list_item { | 120 | struct ctrl_volt_volt_rail_list_item { |
121 | u8 rail_idx; | 121 | u8 rail_idx; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 5965d177..7d729b6e 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -80,8 +80,8 @@ struct fll_descriptor_header { | |||
80 | u8 size; | 80 | u8 size; |
81 | } __packed; | 81 | } __packed; |
82 | 82 | ||
83 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4 | 83 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_4 4U |
84 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6 | 84 | #define FLL_DESCRIPTOR_HEADER_10_SIZE_6 6U |
85 | 85 | ||
86 | struct fll_descriptor_header_10 { | 86 | struct fll_descriptor_header_10 { |
87 | u8 version; | 87 | u8 version; |
@@ -91,7 +91,7 @@ struct fll_descriptor_header_10 { | |||
91 | u16 max_min_freq_mhz; | 91 | u16 max_min_freq_mhz; |
92 | } __packed; | 92 | } __packed; |
93 | 93 | ||
94 | #define FLL_DESCRIPTOR_ENTRY_10_SIZE 15 | 94 | #define FLL_DESCRIPTOR_ENTRY_10_SIZE 15U |
95 | 95 | ||
96 | struct fll_descriptor_entry_10 { | 96 | struct fll_descriptor_entry_10 { |
97 | u8 fll_device_type; | 97 | u8 fll_device_type; |
@@ -161,7 +161,7 @@ struct vin_descriptor_entry_10 { | |||
161 | #define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 | 161 | #define NV_VIN_DESC_VIN_CAL_GAIN_MASK 0xF80 |
162 | #define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 | 162 | #define NV_VIN_DESC_VIN_CAL_GAIN_SHIFT 7 |
163 | 163 | ||
164 | #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07 | 164 | #define VBIOS_CLOCKS_TABLE_1X_HEADER_SIZE_07 0x07U |
165 | struct vbios_clocks_table_1x_header { | 165 | struct vbios_clocks_table_1x_header { |
166 | u8 version; | 166 | u8 version; |
167 | u8 header_size; | 167 | u8 header_size; |
@@ -171,7 +171,7 @@ struct vbios_clocks_table_1x_header { | |||
171 | u16 cntr_sampling_periodms; | 171 | u16 cntr_sampling_periodms; |
172 | } __packed; | 172 | } __packed; |
173 | 173 | ||
174 | #define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09 | 174 | #define VBIOS_CLOCKS_TABLE_35_HEADER_SIZE_09 0x09U |
175 | struct vbios_clocks_table_35_header { | 175 | struct vbios_clocks_table_35_header { |
176 | u8 version; | 176 | u8 version; |
177 | u8 header_size; | 177 | u8 header_size; |
@@ -182,7 +182,7 @@ struct vbios_clocks_table_35_header { | |||
182 | u16 reference_window; | 182 | u16 reference_window; |
183 | } __packed; | 183 | } __packed; |
184 | 184 | ||
185 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09 | 185 | #define VBIOS_CLOCKS_TABLE_1X_ENTRY_SIZE_09 0x09U |
186 | struct vbios_clocks_table_1x_entry { | 186 | struct vbios_clocks_table_1x_entry { |
187 | u8 flags0; | 187 | u8 flags0; |
188 | u16 param0; | 188 | u16 param0; |
@@ -190,7 +190,7 @@ struct vbios_clocks_table_1x_entry { | |||
190 | u16 param2; | 190 | u16 param2; |
191 | } __packed; | 191 | } __packed; |
192 | 192 | ||
193 | #define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0B | 193 | #define VBIOS_CLOCKS_TABLE_35_ENTRY_SIZE_11 0x0BU |
194 | struct vbios_clocks_table_35_entry { | 194 | struct vbios_clocks_table_35_entry { |
195 | u8 flags0; | 195 | u8 flags0; |
196 | u16 param0; | 196 | u16 param0; |
@@ -243,7 +243,7 @@ struct vbios_clocks_table_35_entry { | |||
243 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 | 243 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_MASK 0xFF00 |
244 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 | 244 | #define NV_VBIOS_CLOCKS_TABLE_35_ENTRY_PARAM3_CLK_MONITOR_THRESHOLD_MAX_SHIFT 0x08 |
245 | 245 | ||
246 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08 | 246 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_HEADER_SIZE_08 0x08U |
247 | struct vbios_clock_programming_table_1x_header { | 247 | struct vbios_clock_programming_table_1x_header { |
248 | u8 version; | 248 | u8 version; |
249 | u8 header_size; | 249 | u8 header_size; |
@@ -255,8 +255,8 @@ struct vbios_clock_programming_table_1x_header { | |||
255 | u8 vf_entry_count; | 255 | u8 vf_entry_count; |
256 | } __packed; | 256 | } __packed; |
257 | 257 | ||
258 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05 | 258 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_05 0x05U |
259 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0D | 259 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_SIZE_0D 0x0DU |
260 | struct vbios_clock_programming_table_1x_entry { | 260 | struct vbios_clock_programming_table_1x_entry { |
261 | u8 flags0; | 261 | u8 flags0; |
262 | u16 freq_max_mhz; | 262 | u16 freq_max_mhz; |
@@ -289,7 +289,7 @@ struct vbios_clock_programming_table_1x_entry { | |||
289 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF | 289 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_MASK 0xFF |
290 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 | 290 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_ENTRY_PARAM1_PLL_FREQ_STEP_SIZE_SHIFT 0 |
291 | 291 | ||
292 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03 | 292 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_SIZE_03 0x03U |
293 | struct vbios_clock_programming_table_1x_slave_entry { | 293 | struct vbios_clock_programming_table_1x_slave_entry { |
294 | u8 clk_dom_idx; | 294 | u8 clk_dom_idx; |
295 | u16 param0; | 295 | u16 param0; |
@@ -301,7 +301,7 @@ struct vbios_clock_programming_table_1x_slave_entry { | |||
301 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF | 301 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_MASK 0x3FFF |
302 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 | 302 | #define NV_VBIOS_CLOCK_PROGRAMMING_TABLE_1X_SLAVE_ENTRY_PARAM0_MASTER_TABLE_FREQ_SHIFT 0 |
303 | 303 | ||
304 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02 | 304 | #define VBIOS_CLOCK_PROGRAMMING_TABLE_1X_VF_ENTRY_SIZE_02 0x02U |
305 | struct vbios_clock_programming_table_1x_vf_entry { | 305 | struct vbios_clock_programming_table_1x_vf_entry { |
306 | u8 vfe_idx; | 306 | u8 vfe_idx; |
307 | u8 param0; | 307 | u8 param0; |
@@ -320,8 +320,8 @@ struct vbios_vfe_3x_header_struct { | |||
320 | u8 polling_periodms; | 320 | u8 polling_periodms; |
321 | } __packed; | 321 | } __packed; |
322 | 322 | ||
323 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11 | 323 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_11 0x11U |
324 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19 | 324 | #define VBIOS_VFE_3X_VAR_ENTRY_SIZE_19 0x19U |
325 | struct vbios_vfe_3x_var_entry_struct { | 325 | struct vbios_vfe_3x_var_entry_struct { |
326 | u8 type; | 326 | u8 type; |
327 | u32 out_range_min; | 327 | u32 out_range_min; |
@@ -332,13 +332,13 @@ struct vbios_vfe_3x_var_entry_struct { | |||
332 | u32 param3; | 332 | u32 param3; |
333 | } __packed; | 333 | } __packed; |
334 | 334 | ||
335 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00 | 335 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED 0x00U |
336 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01 | 336 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_FREQUENCY 0x01U |
337 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02 | 337 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_VOLTAGE 0x02U |
338 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03 | 338 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_TEMP 0x03U |
339 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04 | 339 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_SINGLE_SENSED_FUSE 0x04U |
340 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05 | 340 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_PRODUCT 0x05U |
341 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06 | 341 | #define VBIOS_VFE_3X_VAR_ENTRY_TYPE_DERIVED_SUM 0x06U |
342 | 342 | ||
343 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF | 343 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_MASK 0xFF |
344 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 | 344 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSTEMP_TH_CH_IDX_SHIFT 0 |
@@ -387,8 +387,8 @@ struct vbios_vfe_3x_var_entry_struct { | |||
387 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF | 387 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_MASK 0xFFFFFFFF |
388 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 | 388 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR1_SSFUSE_HW_CORRECTION_OFFSET_SHIFT 0 |
389 | 389 | ||
390 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17 | 390 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_17 0x17U |
391 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18 | 391 | #define VBIOS_VFE_3X_EQU_ENTRY_SIZE_18 0x18U |
392 | 392 | ||
393 | struct vbios_vfe_3x_equ_entry_struct { | 393 | struct vbios_vfe_3x_equ_entry_struct { |
394 | u8 type; | 394 | u8 type; |
@@ -403,14 +403,14 @@ struct vbios_vfe_3x_equ_entry_struct { | |||
403 | } __packed; | 403 | } __packed; |
404 | 404 | ||
405 | 405 | ||
406 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00 | 406 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_DISABLED 0x00U |
407 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01 | 407 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC 0x01U |
408 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02 | 408 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX 0x02U |
409 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03 | 409 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_COMPARE 0x03U |
410 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04 | 410 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_QUADRATIC_FXP 0x04U |
411 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05 | 411 | #define VBIOS_VFE_3X_EQU_ENTRY_TYPE_MINMAX_FXP 0x05U |
412 | 412 | ||
413 | #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFF | 413 | #define VBIOS_VFE_3X_EQU_ENTRY_IDX_INVALID 0xFFU |
414 | 414 | ||
415 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF | 415 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_MASK 0xFFFFFFFF |
416 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 | 416 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR0_QUADRATIC_C0_SHIFT 0 |
@@ -452,35 +452,35 @@ struct vbios_vfe_3x_equ_entry_struct { | |||
452 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 | 452 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VF_GAIN 0x3 |
453 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 | 453 | #define VBIOS_VFE_3X_EQU_ENTRY_PAR3_OUTPUT_TYPE_VOLT_DELTA_UV 0x4 |
454 | 454 | ||
455 | #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000 | 455 | #define NV_VFIELD_DESC_SIZE_BYTE 0x00000000U |
456 | #define NV_VFIELD_DESC_SIZE_WORD 0x00000001 | 456 | #define NV_VFIELD_DESC_SIZE_WORD 0x00000001U |
457 | #define NV_VFIELD_DESC_SIZE_DWORD 0x00000002 | 457 | #define NV_VFIELD_DESC_SIZE_DWORD 0x00000002U |
458 | #define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18) >> 3) | 458 | #define VFIELD_SIZE(pvregentry) ((pvregentry->strap_reg_desc & 0x18U) >> 3U) |
459 | 459 | ||
460 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000 | 460 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID 0x00000000U |
461 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001 | 461 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_REG 0x00000001U |
462 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002 | 462 | #define NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG 0x00000002U |
463 | 463 | ||
464 | #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID | 464 | #define NV_VFIELD_DESC_CODE_INVALID NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID |
465 | #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG | 465 | #define NV_VFIELD_DESC_CODE_REG NV_PMU_BIOS_VFIELD_DESC_CODE_REG |
466 | #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG | 466 | #define NV_VFIELD_DESC_CODE_INDEX_REG NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG |
467 | 467 | ||
468 | #define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0) >> 5) | 468 | #define VFIELD_CODE(pvregentry) ((pvregentry->strap_reg_desc & 0xE0U) >> 5U) |
469 | 469 | ||
470 | #define VFIELD_ID_STRAP_IDDQ 0x09 | 470 | #define VFIELD_ID_STRAP_IDDQ 0x09U |
471 | #define VFIELD_ID_STRAP_IDDQ_1 0x0B | 471 | #define VFIELD_ID_STRAP_IDDQ_1 0x0BU |
472 | 472 | ||
473 | #define VFIELD_REG_HEADER_SIZE 3 | 473 | #define VFIELD_REG_HEADER_SIZE 3U |
474 | struct vfield_reg_header { | 474 | struct vfield_reg_header { |
475 | u8 version; | 475 | u8 version; |
476 | u8 entry_size; | 476 | u8 entry_size; |
477 | u8 count; | 477 | u8 count; |
478 | } __packed; | 478 | } __packed; |
479 | 479 | ||
480 | #define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10 | 480 | #define VBIOS_VFIELD_REG_TABLE_VERSION_1_0 0x10U |
481 | 481 | ||
482 | 482 | ||
483 | #define VFIELD_REG_ENTRY_SIZE 13 | 483 | #define VFIELD_REG_ENTRY_SIZE 13U |
484 | struct vfield_reg_entry { | 484 | struct vfield_reg_entry { |
485 | u8 strap_reg_desc; | 485 | u8 strap_reg_desc; |
486 | u32 reg; | 486 | u32 reg; |
@@ -488,7 +488,7 @@ struct vfield_reg_entry { | |||
488 | u32 index; | 488 | u32 index; |
489 | } __packed; | 489 | } __packed; |
490 | 490 | ||
491 | #define VFIELD_HEADER_SIZE 3 | 491 | #define VFIELD_HEADER_SIZE 3U |
492 | 492 | ||
493 | struct vfield_header { | 493 | struct vfield_header { |
494 | u8 version; | 494 | u8 version; |
@@ -496,24 +496,24 @@ struct vfield_header { | |||
496 | u8 count; | 496 | u8 count; |
497 | } __packed; | 497 | } __packed; |
498 | 498 | ||
499 | #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10 | 499 | #define VBIOS_VFIELD_TABLE_VERSION_1_0 0x10U |
500 | 500 | ||
501 | #define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1F) | 501 | #define VFIELD_BIT_START(ventry) (ventry.strap_desc & 0x1FU) |
502 | #define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0) >> 5) | 502 | #define VFIELD_BIT_STOP(ventry) ((ventry.strap_desc & 0x3E0U) >> 5U) |
503 | #define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00) >> 10) | 503 | #define VFIELD_BIT_REG(ventry) ((ventry.strap_desc & 0x3C00U) >> 10U) |
504 | 504 | ||
505 | #define VFIELD_ENTRY_SIZE 3 | 505 | #define VFIELD_ENTRY_SIZE 3U |
506 | 506 | ||
507 | struct vfield_entry { | 507 | struct vfield_entry { |
508 | u8 strap_id; | 508 | u8 strap_id; |
509 | u16 strap_desc; | 509 | u16 strap_desc; |
510 | } __packed; | 510 | } __packed; |
511 | 511 | ||
512 | #define PERF_CLK_DOMAINS_IDX_MAX (32) | 512 | #define PERF_CLK_DOMAINS_IDX_MAX (32U) |
513 | #define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX | 513 | #define PERF_CLK_DOMAINS_IDX_INVALID PERF_CLK_DOMAINS_IDX_MAX |
514 | 514 | ||
515 | #define VBIOS_PSTATE_TABLE_VERSION_5X 0x50 | 515 | #define VBIOS_PSTATE_TABLE_VERSION_5X 0x50U |
516 | #define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10) | 516 | #define VBIOS_PSTATE_HEADER_5X_SIZE_10 (10U) |
517 | 517 | ||
518 | struct vbios_pstate_header_5x { | 518 | struct vbios_pstate_header_5x { |
519 | u8 version; | 519 | u8 version; |
@@ -528,10 +528,10 @@ struct vbios_pstate_header_5x { | |||
528 | u8 cpi_features; | 528 | u8 cpi_features; |
529 | } __packed; | 529 | } __packed; |
530 | 530 | ||
531 | #define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6 | 531 | #define VBIOS_PSTATE_CLOCK_ENTRY_5X_SIZE_6 6U |
532 | 532 | ||
533 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2 | 533 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_2 0x2U |
534 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3 | 534 | #define VBIOS_PSTATE_BASE_ENTRY_5X_SIZE_3 0x3U |
535 | 535 | ||
536 | struct vbios_pstate_entry_clock_5x { | 536 | struct vbios_pstate_entry_clock_5x { |
537 | u16 param0; | 537 | u16 param0; |
@@ -554,13 +554,13 @@ struct vbios_pstate_entry_5x { | |||
554 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 | 554 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_SHIFT 14 |
555 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 | 555 | #define VBIOS_PSTATE_5X_CLOCK_PROG_PARAM1_MAX_FREQ_MHZ_MASK 0x0FFFC000 |
556 | 556 | ||
557 | #define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFF | 557 | #define VBIOS_PERFLEVEL_SKIP_ENTRY 0xFFU |
558 | 558 | ||
559 | #define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11 | 559 | #define VBIOS_MEMORY_CLOCK_HEADER_11_VERSION 0x11U |
560 | 560 | ||
561 | #define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16 | 561 | #define VBIOS_MEMORY_CLOCK_HEADER_11_0_SIZE 16U |
562 | #define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21 | 562 | #define VBIOS_MEMORY_CLOCK_HEADER_11_1_SIZE 21U |
563 | #define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26 | 563 | #define VBIOS_MEMORY_CLOCK_HEADER_11_2_SIZE 26U |
564 | 564 | ||
565 | struct vbios_memory_clock_header_1x { | 565 | struct vbios_memory_clock_header_1x { |
566 | u8 version; | 566 | u8 version; |
@@ -580,7 +580,7 @@ struct vbios_memory_clock_header_1x { | |||
580 | u8 cmd_script_list_count; | 580 | u8 cmd_script_list_count; |
581 | } __packed; | 581 | } __packed; |
582 | 582 | ||
583 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20 | 583 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_2_SIZE 20U |
584 | 584 | ||
585 | struct vbios_memory_clock_base_entry_11 { | 585 | struct vbios_memory_clock_base_entry_11 { |
586 | u16 minimum; | 586 | u16 minimum; |
@@ -604,8 +604,8 @@ struct vbios_memory_clock_base_entry_11 { | |||
604 | ((u8)0x3) | 604 | ((u8)0x3) |
605 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 | 605 | #define VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX_SHIFT 0 |
606 | 606 | ||
607 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20 | 607 | #define VBIOS_POWER_SENSORS_VERSION_2X 0x20U |
608 | #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008 | 608 | #define VBIOS_POWER_SENSORS_2X_HEADER_SIZE_08 0x00000008U |
609 | 609 | ||
610 | struct pwr_sensors_2x_header { | 610 | struct pwr_sensors_2x_header { |
611 | u8 version; | 611 | u8 version; |
@@ -615,7 +615,7 @@ struct pwr_sensors_2x_header { | |||
615 | u32 ba_script_pointer; | 615 | u32 ba_script_pointer; |
616 | } __packed; | 616 | } __packed; |
617 | 617 | ||
618 | #define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015 | 618 | #define VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 0x00000015U |
619 | 619 | ||
620 | struct pwr_sensors_2x_entry { | 620 | struct pwr_sensors_2x_entry { |
621 | u8 flags0; | 621 | u8 flags0; |
@@ -628,7 +628,7 @@ struct pwr_sensors_2x_entry { | |||
628 | 628 | ||
629 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | 629 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_MASK 0xF |
630 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | 630 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 |
631 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001 | 631 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_FLAGS0_CLASS_I2C 0x00000001U |
632 | 632 | ||
633 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF | 633 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_MASK 0xFF |
634 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 | 634 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_CLASS_PARAM0_I2C_INDEX_SHIFT 0 |
@@ -653,8 +653,8 @@ struct pwr_sensors_2x_entry { | |||
653 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 | 653 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_MASK 0xFFFF0000 |
654 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 | 654 | #define NV_VBIOS_POWER_SENSORS_2X_ENTRY_SENSOR_PARAM3_INA3221_CURR_CORRECT_B_SHIFT 16 |
655 | 655 | ||
656 | #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20 | 656 | #define VBIOS_POWER_TOPOLOGY_VERSION_2X 0x20U |
657 | #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006 | 657 | #define VBIOS_POWER_TOPOLOGY_2X_HEADER_SIZE_06 0x00000006U |
658 | 658 | ||
659 | struct pwr_topology_2x_header { | 659 | struct pwr_topology_2x_header { |
660 | u8 version; | 660 | u8 version; |
@@ -665,7 +665,7 @@ struct pwr_topology_2x_header { | |||
665 | u8 num_rel_entries; | 665 | u8 num_rel_entries; |
666 | } __packed; | 666 | } __packed; |
667 | 667 | ||
668 | #define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016 | 668 | #define VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 0x00000016U |
669 | 669 | ||
670 | struct pwr_topology_2x_entry { | 670 | struct pwr_topology_2x_entry { |
671 | u8 flags0; | 671 | u8 flags0; |
@@ -679,15 +679,15 @@ struct pwr_topology_2x_entry { | |||
679 | 679 | ||
680 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF | 680 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_MASK 0xF |
681 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 | 681 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SHIFT 0 |
682 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR 0x00000001 | 682 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_FLAGS0_CLASS_SENSOR U8(0x00000001) |
683 | 683 | ||
684 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF | 684 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_MASK 0xFF |
685 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 | 685 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_INDEX_SHIFT 0 |
686 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 | 686 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_MASK 0xFF00 |
687 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 | 687 | #define NV_VBIOS_POWER_TOPOLOGY_2X_ENTRY_PARAM1_SENSOR_PROVIDER_INDEX_SHIFT 8 |
688 | 688 | ||
689 | #define VBIOS_POWER_POLICY_VERSION_3X 0x30 | 689 | #define VBIOS_POWER_POLICY_VERSION_3X 0x30U |
690 | #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025 | 690 | #define VBIOS_POWER_POLICY_3X_HEADER_SIZE_25 0x00000025U |
691 | 691 | ||
692 | struct pwr_policy_3x_header_struct { | 692 | struct pwr_policy_3x_header_struct { |
693 | u8 version; | 693 | u8 version; |
@@ -714,7 +714,7 @@ struct pwr_policy_3x_header_struct { | |||
714 | u8 num_table_viol_entries; | 714 | u8 num_table_viol_entries; |
715 | } __packed; | 715 | } __packed; |
716 | 716 | ||
717 | #define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002E | 717 | #define VBIOS_POWER_POLICY_3X_ENTRY_SIZE_2E 0x0000002EU |
718 | 718 | ||
719 | struct pwr_policy_3x_entry_struct { | 719 | struct pwr_policy_3x_entry_struct { |
720 | u8 flags0; | 720 | u8 flags0; |
@@ -738,7 +738,7 @@ struct pwr_policy_3x_entry_struct { | |||
738 | 738 | ||
739 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF | 739 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_MASK 0xF |
740 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 | 740 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_SHIFT 0 |
741 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005 | 741 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_CLASS_HW_THRESHOLD 0x00000005U |
742 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 | 742 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_MASK 0x10 |
743 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 | 743 | #define NV_VBIOS_POWER_POLICY_3X_ENTRY_FLAGS0_LIMIT_UNIT_SHIFT 4 |
744 | 744 | ||
@@ -768,12 +768,12 @@ struct vbios_voltage_rail_table_1x_header { | |||
768 | u8 volt_domain_hal; | 768 | u8 volt_domain_hal; |
769 | } __packed; | 769 | } __packed; |
770 | 770 | ||
771 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007 | 771 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007U |
772 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008 | 772 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008U |
773 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009 | 773 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009U |
774 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A | 774 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000AU |
775 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B | 775 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000BU |
776 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000C | 776 | #define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0C 0X0000000CU |
777 | 777 | ||
778 | struct vbios_voltage_rail_table_1x_entry { | 778 | struct vbios_voltage_rail_table_1x_entry { |
779 | u32 boot_voltage_uv; | 779 | u32 boot_voltage_uv; |
@@ -806,8 +806,8 @@ struct vbios_voltage_device_table_1x_entry { | |||
806 | u32 param4; | 806 | u32 param4; |
807 | } __packed; | 807 | } __packed; |
808 | 808 | ||
809 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00 | 809 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00U |
810 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02 | 810 | #define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02U |
811 | 811 | ||
812 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ | 812 | #define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \ |
813 | GENMASK(23, 0) | 813 | GENMASK(23, 0) |
@@ -865,11 +865,11 @@ struct vbios_voltage_policy_table_1x_entry { | |||
865 | u32 param3; | 865 | u32 param3; |
866 | } __packed; | 866 | } __packed; |
867 | 867 | ||
868 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00 | 868 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00U |
869 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01 | 869 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01U |
870 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02 | 870 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02U |
871 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03 | 871 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03U |
872 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04 | 872 | #define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL_MULTI_STEP 0x04U |
873 | 873 | ||
874 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ | 874 | #define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \ |
875 | GENMASK(7, 0) | 875 | GENMASK(7, 0) |
@@ -906,9 +906,9 @@ struct vbios_voltage_policy_table_1x_entry { | |||
906 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ | 906 | #define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \ |
907 | 0 | 907 | 0 |
908 | 908 | ||
909 | #define VBIOS_THERM_DEVICE_VERSION_1X 0x10 | 909 | #define VBIOS_THERM_DEVICE_VERSION_1X 0x10U |
910 | 910 | ||
911 | #define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004 | 911 | #define VBIOS_THERM_DEVICE_1X_HEADER_SIZE_04 0x00000004U |
912 | 912 | ||
913 | struct therm_device_1x_header { | 913 | struct therm_device_1x_header { |
914 | u8 version; | 914 | u8 version; |
@@ -923,19 +923,19 @@ struct therm_device_1x_entry { | |||
923 | u8 flags; | 923 | u8 flags; |
924 | } ; | 924 | } ; |
925 | 925 | ||
926 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00 | 926 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_INVALID 0x00U |
927 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01 | 927 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU 0x01U |
928 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02 | 928 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_TSOSC 0x02U |
929 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03 | 929 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_GPU_GPC_SCI 0x03U |
930 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70 | 930 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_SITE 0x70U |
931 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71 | 931 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_CLASS_HBM2_COMBINED 0x71U |
932 | 932 | ||
933 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF | 933 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_MASK 0xFF |
934 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 | 934 | #define NV_VBIOS_THERM_DEVICE_1X_ENTRY_PARAM0_I2C_DEVICE_INDEX_SHIFT 0 |
935 | 935 | ||
936 | #define VBIOS_THERM_CHANNEL_VERSION_1X 0x10 | 936 | #define VBIOS_THERM_CHANNEL_VERSION_1X 0x10U |
937 | 937 | ||
938 | #define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009 | 938 | #define VBIOS_THERM_CHANNEL_1X_HEADER_SIZE_09 0x00000009U |
939 | 939 | ||
940 | struct therm_channel_1x_header { | 940 | struct therm_channel_1x_header { |
941 | u8 version; | 941 | u8 version; |
@@ -957,7 +957,7 @@ struct therm_channel_1x_entry { | |||
957 | u8 flags; | 957 | u8 flags; |
958 | } __packed; | 958 | } __packed; |
959 | 959 | ||
960 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01 | 960 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_CLASS_DEVICE 0x01U |
961 | 961 | ||
962 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF | 962 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_MASK 0xFF |
963 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 | 963 | #define NV_VBIOS_THERM_CHANNEL_1X_ENTRY_PARAM0_DEVICE_INDEX_SHIFT 0 |
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c index fccd3b03..bb5d1821 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.c +++ b/drivers/gpu/nvgpu/volt/volt_dev.c | |||
@@ -35,8 +35,8 @@ | |||
35 | 35 | ||
36 | #include "volt.h" | 36 | #include "volt.h" |
37 | 37 | ||
38 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 | 38 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0U |
39 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 | 39 | #define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1U |
40 | 40 | ||
41 | static int volt_device_pmu_data_init_super(struct gk20a *g, | 41 | static int volt_device_pmu_data_init_super(struct gk20a *g, |
42 | struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) | 42 | struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata) |
@@ -425,7 +425,7 @@ static int _volt_device_devgrp_pmudata_instget(struct gk20a *g, | |||
425 | 425 | ||
426 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 426 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
427 | if (((u32)BIT(idx) & | 427 | if (((u32)BIT(idx) & |
428 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { | 428 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
429 | return -EINVAL; | 429 | return -EINVAL; |
430 | } | 430 | } |
431 | 431 | ||
@@ -445,7 +445,7 @@ static int _volt_device_devgrp_pmustatus_instget(struct gk20a *g, | |||
445 | 445 | ||
446 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 446 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
447 | if (((u32)BIT(idx) & | 447 | if (((u32)BIT(idx) & |
448 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { | 448 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
449 | return -EINVAL; | 449 | return -EINVAL; |
450 | } | 450 | } |
451 | 451 | ||
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.h b/drivers/gpu/nvgpu/volt/volt_dev.h index eb1868cb..48d93aea 100644 --- a/drivers/gpu/nvgpu/volt/volt_dev.h +++ b/drivers/gpu/nvgpu/volt/volt_dev.h | |||
@@ -27,8 +27,8 @@ | |||
27 | #include "boardobj/boardobjgrp.h" | 27 | #include "boardobj/boardobjgrp.h" |
28 | #include "ctrl/ctrlvolt.h" | 28 | #include "ctrl/ctrlvolt.h" |
29 | 29 | ||
30 | #define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1 | 30 | #define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1U |
31 | #define VOLTAGE_TABLE_MAX_ENTRIES 256 | 31 | #define VOLTAGE_TABLE_MAX_ENTRIES 256U |
32 | 32 | ||
33 | struct voltage_device { | 33 | struct voltage_device { |
34 | struct boardobj super; | 34 | struct boardobj super; |
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c index 184aa5d0..2249ae24 100644 --- a/drivers/gpu/nvgpu/volt/volt_pmu.c +++ b/drivers/gpu/nvgpu/volt/volt_pmu.c | |||
@@ -108,7 +108,7 @@ static u32 volt_pmu_rpc_execute(struct gk20a *g, | |||
108 | gk20a_get_gr_idle_timeout(g), | 108 | gk20a_get_gr_idle_timeout(g), |
109 | &handler.success, 1); | 109 | &handler.success, 1); |
110 | 110 | ||
111 | if (handler.success == 0) { | 111 | if (handler.success == 0U) { |
112 | status = -EINVAL; | 112 | status = -EINVAL; |
113 | nvgpu_err(g, "rpc call to volt failed"); | 113 | nvgpu_err(g, "rpc call to volt failed"); |
114 | } | 114 | } |
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c index 4f9d7ad8..cc60730d 100644 --- a/drivers/gpu/nvgpu/volt/volt_policy.c +++ b/drivers/gpu/nvgpu/volt/volt_policy.c | |||
@@ -382,7 +382,7 @@ static int _volt_policy_devgrp_pmudata_instget(struct gk20a *g, | |||
382 | 382 | ||
383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
384 | if (((u32)BIT(idx) & | 384 | if (((u32)BIT(idx) & |
385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { | 385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
386 | return -EINVAL; | 386 | return -EINVAL; |
387 | } | 387 | } |
388 | 388 | ||
@@ -402,7 +402,7 @@ static int _volt_policy_devgrp_pmustatus_instget(struct gk20a *g, | |||
402 | 402 | ||
403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
404 | if (((u32)BIT(idx) & | 404 | if (((u32)BIT(idx) & |
405 | p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { | 405 | p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
406 | return -EINVAL; | 406 | return -EINVAL; |
407 | } | 407 | } |
408 | 408 | ||
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c index 37e85761..caf297f0 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.c +++ b/drivers/gpu/nvgpu/volt/volt_rail.c | |||
@@ -105,7 +105,7 @@ static u32 volt_rail_state_init(struct gk20a *g, | |||
105 | pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; | 105 | pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID; |
106 | 106 | ||
107 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | 107 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { |
108 | pvolt_rail->volt_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV; | 108 | pvolt_rail->volt_delta_uv[i] = (int)NV_PMU_VOLT_VALUE_0V_IN_UV; |
109 | g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] = | 109 | g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] = |
110 | NV_PMU_VOLT_VALUE_0V_IN_UV; | 110 | NV_PMU_VOLT_VALUE_0V_IN_UV; |
111 | } | 111 | } |
@@ -162,7 +162,7 @@ static int volt_rail_init_pmudata_super(struct gk20a *g, | |||
162 | 162 | ||
163 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { | 163 | for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) { |
164 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + | 164 | rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] + |
165 | g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; | 165 | (int)g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i]; |
166 | } | 166 | } |
167 | 167 | ||
168 | status = boardobjgrpmask_export(&prail->volt_dev_mask.super, | 168 | status = boardobjgrpmask_export(&prail->volt_dev_mask.super, |
@@ -225,7 +225,7 @@ u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g, | |||
225 | { | 225 | { |
226 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { | 226 | switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) { |
227 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: | 227 | case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL: |
228 | if (vbios_volt_domain == 0) { | 228 | if (vbios_volt_domain == 0U) { |
229 | return CTRL_VOLT_DOMAIN_LOGIC; | 229 | return CTRL_VOLT_DOMAIN_LOGIC; |
230 | } | 230 | } |
231 | break; | 231 | break; |
@@ -382,7 +382,7 @@ static int _volt_rail_devgrp_pmudata_instget(struct gk20a *g, | |||
382 | 382 | ||
383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 383 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
384 | if (((u32)BIT(idx) & | 384 | if (((u32)BIT(idx) & |
385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0) { | 385 | pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
386 | return -EINVAL; | 386 | return -EINVAL; |
387 | } | 387 | } |
388 | 388 | ||
@@ -402,7 +402,7 @@ static int _volt_rail_devgrp_pmustatus_instget(struct gk20a *g, | |||
402 | 402 | ||
403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ | 403 | /*check whether pmuboardobjgrp has a valid boardobj in index*/ |
404 | if (((u32)BIT(idx) & | 404 | if (((u32)BIT(idx) & |
405 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0) { | 405 | pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0U) { |
406 | return -EINVAL; | 406 | return -EINVAL; |
407 | } | 407 | } |
408 | 408 | ||
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h index 522d635a..72bb2546 100644 --- a/drivers/gpu/nvgpu/volt/volt_rail.h +++ b/drivers/gpu/nvgpu/volt/volt_rail.h | |||
@@ -27,8 +27,8 @@ | |||
27 | #include "boardobj/boardobj.h" | 27 | #include "boardobj/boardobj.h" |
28 | #include "boardobj/boardobjgrp.h" | 28 | #include "boardobj/boardobjgrp.h" |
29 | 29 | ||
30 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04 | 30 | #define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04U |
31 | #define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFF | 31 | #define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFFU |
32 | 32 | ||
33 | #define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \ | 33 | #define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \ |
34 | ((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ | 34 | ((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \ |