diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | 76 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | 18 |
5 files changed, 142 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h index 2078bdca..1fee19b1 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fb_gp10b.h | |||
@@ -426,10 +426,18 @@ static inline u32 fb_mmu_debug_ctrl_debug_v(u32 r) | |||
426 | { | 426 | { |
427 | return (r >> 16) & 0x1; | 427 | return (r >> 16) & 0x1; |
428 | } | 428 | } |
429 | static inline u32 fb_mmu_debug_ctrl_debug_m(void) | ||
430 | { | ||
431 | return 0x1 << 16; | ||
432 | } | ||
429 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) | 433 | static inline u32 fb_mmu_debug_ctrl_debug_enabled_v(void) |
430 | { | 434 | { |
431 | return 0x00000001; | 435 | return 0x00000001; |
432 | } | 436 | } |
437 | static inline u32 fb_mmu_debug_ctrl_debug_disabled_v(void) | ||
438 | { | ||
439 | return 0x00000000; | ||
440 | } | ||
433 | static inline u32 fb_mmu_vpr_info_r(void) | 441 | static inline u32 fb_mmu_vpr_info_r(void) |
434 | { | 442 | { |
435 | return 0x00100cd0; | 443 | return 0x00100cd0; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h index 2c0367d5..6f7e09ff 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fifo_gp10b.h | |||
@@ -210,10 +210,22 @@ static inline u32 fifo_intr_en_0_r(void) | |||
210 | { | 210 | { |
211 | return 0x00002140; | 211 | return 0x00002140; |
212 | } | 212 | } |
213 | static inline u32 fifo_intr_en_0_sched_error_f(u32 v) | ||
214 | { | ||
215 | return (v & 0x1) << 8; | ||
216 | } | ||
213 | static inline u32 fifo_intr_en_0_sched_error_m(void) | 217 | static inline u32 fifo_intr_en_0_sched_error_m(void) |
214 | { | 218 | { |
215 | return 0x1 << 8; | 219 | return 0x1 << 8; |
216 | } | 220 | } |
221 | static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) | ||
222 | { | ||
223 | return (v & 0x1) << 28; | ||
224 | } | ||
225 | static inline u32 fifo_intr_en_0_mmu_fault_m(void) | ||
226 | { | ||
227 | return 0x1 << 28; | ||
228 | } | ||
217 | static inline u32 fifo_intr_en_1_r(void) | 229 | static inline u32 fifo_intr_en_1_r(void) |
218 | { | 230 | { |
219 | return 0x00002528; | 231 | return 0x00002528; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h index cdb28d08..b6b68718 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_fuse_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -98,4 +98,32 @@ static inline u32 fuse_ctrl_opt_ram_svop_pdp_override_data_no_f(void) | |||
98 | { | 98 | { |
99 | return 0x0; | 99 | return 0x0; |
100 | } | 100 | } |
101 | static inline u32 fuse_status_opt_fbio_r(void) | ||
102 | { | ||
103 | return 0x00021c14; | ||
104 | } | ||
105 | static inline u32 fuse_status_opt_fbio_data_f(u32 v) | ||
106 | { | ||
107 | return (v & 0xffff) << 0; | ||
108 | } | ||
109 | static inline u32 fuse_status_opt_fbio_data_m(void) | ||
110 | { | ||
111 | return 0xffff << 0; | ||
112 | } | ||
113 | static inline u32 fuse_status_opt_fbio_data_v(u32 r) | ||
114 | { | ||
115 | return (r >> 0) & 0xffff; | ||
116 | } | ||
117 | static inline u32 fuse_status_opt_rop_l2_fbp_r(u32 i) | ||
118 | { | ||
119 | return 0x00021d70 + i*4; | ||
120 | } | ||
121 | static inline u32 fuse_status_opt_fbp_r(void) | ||
122 | { | ||
123 | return 0x00021d38; | ||
124 | } | ||
125 | static inline u32 fuse_status_opt_fbp_idx_v(u32 r, u32 i) | ||
126 | { | ||
127 | return (r >> (0 + i*0)) & 0x1; | ||
128 | } | ||
101 | #endif | 129 | #endif |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h index 3cac1f70..72f1d68c 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h | |||
@@ -170,6 +170,10 @@ static inline u32 gr_exception_memfmt_m(void) | |||
170 | { | 170 | { |
171 | return 0x1 << 1; | 171 | return 0x1 << 1; |
172 | } | 172 | } |
173 | static inline u32 gr_exception_ds_m(void) | ||
174 | { | ||
175 | return 0x1 << 4; | ||
176 | } | ||
173 | static inline u32 gr_exception1_r(void) | 177 | static inline u32 gr_exception1_r(void) |
174 | { | 178 | { |
175 | return 0x00400118; | 179 | return 0x00400118; |
@@ -330,6 +334,30 @@ static inline u32 gr_activity_4_r(void) | |||
330 | { | 334 | { |
331 | return 0x00400390; | 335 | return 0x00400390; |
332 | } | 336 | } |
337 | static inline u32 gr_pri_gpc0_gcc_dbg_r(void) | ||
338 | { | ||
339 | return 0x00501000; | ||
340 | } | ||
341 | static inline u32 gr_pri_gpcs_gcc_dbg_r(void) | ||
342 | { | ||
343 | return 0x00419000; | ||
344 | } | ||
345 | static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | ||
346 | { | ||
347 | return 0x1 << 1; | ||
348 | } | ||
349 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | ||
350 | { | ||
351 | return 0x005046a4; | ||
352 | } | ||
353 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | ||
354 | { | ||
355 | return 0x00419ea4; | ||
356 | } | ||
357 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | ||
358 | { | ||
359 | return 0x1 << 0; | ||
360 | } | ||
333 | static inline u32 gr_pri_sked_activity_r(void) | 361 | static inline u32 gr_pri_sked_activity_r(void) |
334 | { | 362 | { |
335 | return 0x00407054; | 363 | return 0x00407054; |
@@ -3058,6 +3086,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_r(void) | |||
3058 | { | 3086 | { |
3059 | return 0x0050450c; | 3087 | return 0x0050450c; |
3060 | } | 3088 | } |
3089 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) | ||
3090 | { | ||
3091 | return (r >> 1) & 0x1; | ||
3092 | } | ||
3061 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | 3093 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) |
3062 | { | 3094 | { |
3063 | return 0x2; | 3095 | return 0x2; |
@@ -3106,6 +3138,10 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_on_v(void) | |||
3106 | { | 3138 | { |
3107 | return 0x00000001; | 3139 | return 0x00000001; |
3108 | } | 3140 | } |
3141 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_debugger_mode_off_v(void) | ||
3142 | { | ||
3143 | return 0x00000000; | ||
3144 | } | ||
3109 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) | 3145 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_trigger_enable_f(void) |
3110 | { | 3146 | { |
3111 | return 0x80000000; | 3147 | return 0x80000000; |
@@ -3118,10 +3154,50 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | |||
3118 | { | 3154 | { |
3119 | return 0x40000000; | 3155 | return 0x40000000; |
3120 | } | 3156 | } |
3157 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | ||
3158 | { | ||
3159 | return (r >> 1) & 0x1; | ||
3160 | } | ||
3161 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | ||
3162 | { | ||
3163 | return 0x0; | ||
3164 | } | ||
3165 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | ||
3166 | { | ||
3167 | return (r >> 2) & 0x1; | ||
3168 | } | ||
3169 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | ||
3170 | { | ||
3171 | return 0x0; | ||
3172 | } | ||
3173 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3174 | { | ||
3175 | return 0x00504614; | ||
3176 | } | ||
3177 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) | ||
3178 | { | ||
3179 | return 0x00504624; | ||
3180 | } | ||
3181 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | ||
3182 | { | ||
3183 | return 0x00504634; | ||
3184 | } | ||
3185 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | ||
3186 | { | ||
3187 | return 0x00000000; | ||
3188 | } | ||
3189 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | ||
3190 | { | ||
3191 | return 0x00000000; | ||
3192 | } | ||
3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3193 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3122 | { | 3194 | { |
3123 | return 0x0050460c; | 3195 | return 0x0050460c; |
3124 | } | 3196 | } |
3197 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3198 | { | ||
3199 | return (r >> 0) & 0x1; | ||
3200 | } | ||
3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) | 3201 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) |
3126 | { | 3202 | { |
3127 | return (r >> 4) & 0x1; | 3203 | return (r >> 4) & 0x1; |
diff --git a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h index 0982bc09..ab6f6373 100644 --- a/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/hw_top_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -74,6 +74,22 @@ static inline u32 top_num_fbps_value_v(u32 r) | |||
74 | { | 74 | { |
75 | return (r >> 0) & 0x1f; | 75 | return (r >> 0) & 0x1f; |
76 | } | 76 | } |
77 | static inline u32 top_ltc_per_fbp_r(void) | ||
78 | { | ||
79 | return 0x00022450; | ||
80 | } | ||
81 | static inline u32 top_ltc_per_fbp_value_v(u32 r) | ||
82 | { | ||
83 | return (r >> 0) & 0x1f; | ||
84 | } | ||
85 | static inline u32 top_slices_per_ltc_r(void) | ||
86 | { | ||
87 | return 0x0002245c; | ||
88 | } | ||
89 | static inline u32 top_slices_per_ltc_value_v(u32 r) | ||
90 | { | ||
91 | return (r >> 0) & 0x1f; | ||
92 | } | ||
77 | static inline u32 top_num_ltcs_r(void) | 93 | static inline u32 top_num_ltcs_r(void) |
78 | { | 94 | { |
79 | return 0x00022454; | 95 | return 0x00022454; |