diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.c | 65 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/mc_gp10b.h | 7 |
2 files changed, 50 insertions, 22 deletions
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 3fae4ea3..c7a4bc75 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -23,17 +23,44 @@ void mc_gp10b_intr_enable(struct gk20a *g) | |||
23 | { | 23 | { |
24 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | 24 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); |
25 | 25 | ||
26 | gk20a_writel(g, mc_intr_en_clear_r(0), 0xffffffff); | 26 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_STALLING), |
27 | gk20a_writel(g, mc_intr_en_set_r(0), | 27 | 0xffffffff); |
28 | mc_intr_pfifo_pending_f() | 28 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING] = |
29 | | eng_intr_mask); | 29 | mc_intr_pfifo_pending_f() |
30 | gk20a_writel(g, mc_intr_en_clear_r(1), 0xffffffff); | 30 | | eng_intr_mask; |
31 | gk20a_writel(g, mc_intr_en_set_r(1), | 31 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
32 | mc_intr_pfifo_pending_f() | 32 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
33 | | mc_intr_priv_ring_pending_f() | 33 | |
34 | | mc_intr_ltc_pending_f() | 34 | gk20a_writel(g, mc_intr_en_clear_r(NVGPU_MC_INTR_NONSTALLING), |
35 | | mc_intr_pbus_pending_f() | 35 | 0xffffffff); |
36 | | eng_intr_mask); | 36 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING] = |
37 | mc_intr_pfifo_pending_f() | ||
38 | | mc_intr_priv_ring_pending_f() | ||
39 | | mc_intr_ltc_pending_f() | ||
40 | | mc_intr_pbus_pending_f() | ||
41 | | eng_intr_mask; | ||
42 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), | ||
43 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); | ||
44 | } | ||
45 | |||
46 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | ||
47 | bool is_stalling, u32 mask) | ||
48 | { | ||
49 | u32 intr_index = 0; | ||
50 | u32 reg = 0; | ||
51 | |||
52 | intr_index = (is_stalling ? NVGPU_MC_INTR_STALLING : | ||
53 | NVGPU_MC_INTR_NONSTALLING); | ||
54 | if (enable) { | ||
55 | reg = mc_intr_en_set_r(intr_index); | ||
56 | g->ops.mc.intr_mask_restore[intr_index] |= mask; | ||
57 | |||
58 | } else { | ||
59 | reg = mc_intr_en_clear_r(intr_index); | ||
60 | g->ops.mc.intr_mask_restore[intr_index] &= ~mask; | ||
61 | } | ||
62 | |||
63 | gk20a_writel(g, reg, mask); | ||
37 | } | 64 | } |
38 | 65 | ||
39 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) | 66 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g) |
@@ -73,7 +100,6 @@ irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g) | |||
73 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | 100 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) |
74 | { | 101 | { |
75 | u32 mc_intr_0; | 102 | u32 mc_intr_0; |
76 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
77 | 103 | ||
78 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 104 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
79 | 105 | ||
@@ -94,9 +120,8 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
94 | if (mc_intr_0 & mc_intr_pbus_pending_f()) | 120 | if (mc_intr_0 & mc_intr_pbus_pending_f()) |
95 | gk20a_pbus_isr(g); | 121 | gk20a_pbus_isr(g); |
96 | 122 | ||
97 | gk20a_writel(g, mc_intr_en_set_r(0), | 123 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_STALLING), |
98 | mc_intr_pfifo_pending_f() | 124 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_STALLING]); |
99 | | eng_intr_mask); | ||
100 | 125 | ||
101 | return IRQ_HANDLED; | 126 | return IRQ_HANDLED; |
102 | } | 127 | } |
@@ -104,7 +129,6 @@ irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g) | |||
104 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | 129 | irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) |
105 | { | 130 | { |
106 | u32 mc_intr_1; | 131 | u32 mc_intr_1; |
107 | u32 eng_intr_mask = gk20a_fifo_engine_interrupt_mask(g); | ||
108 | 132 | ||
109 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); | 133 | gk20a_dbg(gpu_dbg_intr, "interrupt thread launched"); |
110 | 134 | ||
@@ -117,12 +141,8 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
117 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 141 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
118 | gk20a_gr_nonstall_isr(g); | 142 | gk20a_gr_nonstall_isr(g); |
119 | 143 | ||
120 | gk20a_writel(g, mc_intr_en_set_r(1), | 144 | gk20a_writel(g, mc_intr_en_set_r(NVGPU_MC_INTR_NONSTALLING), |
121 | mc_intr_pfifo_pending_f() | 145 | g->ops.mc.intr_mask_restore[NVGPU_MC_INTR_NONSTALLING]); |
122 | | mc_intr_priv_ring_pending_f() | ||
123 | | mc_intr_ltc_pending_f() | ||
124 | | mc_intr_pbus_pending_f() | ||
125 | | eng_intr_mask); | ||
126 | 146 | ||
127 | return IRQ_HANDLED; | 147 | return IRQ_HANDLED; |
128 | } | 148 | } |
@@ -130,6 +150,7 @@ irqreturn_t mc_gp10b_intr_thread_nonstall(struct gk20a *g) | |||
130 | void gp10b_init_mc(struct gpu_ops *gops) | 150 | void gp10b_init_mc(struct gpu_ops *gops) |
131 | { | 151 | { |
132 | gops->mc.intr_enable = mc_gp10b_intr_enable; | 152 | gops->mc.intr_enable = mc_gp10b_intr_enable; |
153 | gops->mc.intr_unit_config = mc_gp10b_intr_unit_config; | ||
133 | gops->mc.isr_stall = mc_gp10b_isr_stall; | 154 | gops->mc.isr_stall = mc_gp10b_isr_stall; |
134 | gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; | 155 | gops->mc.isr_nonstall = mc_gp10b_isr_nonstall; |
135 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; | 156 | gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall; |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h index f274ce05..b2ec4be4 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.h | |||
@@ -15,8 +15,15 @@ | |||
15 | #define MC_GP20B_H | 15 | #define MC_GP20B_H |
16 | struct gk20a; | 16 | struct gk20a; |
17 | 17 | ||
18 | enum MC_INTERRUPT_REGLIST { | ||
19 | NVGPU_MC_INTR_STALLING = 0, | ||
20 | NVGPU_MC_INTR_NONSTALLING, | ||
21 | }; | ||
22 | |||
18 | void gp10b_init_mc(struct gpu_ops *gops); | 23 | void gp10b_init_mc(struct gpu_ops *gops); |
19 | void mc_gp10b_intr_enable(struct gk20a *g); | 24 | void mc_gp10b_intr_enable(struct gk20a *g); |
25 | void mc_gp10b_intr_unit_config(struct gk20a *g, bool enable, | ||
26 | bool is_stalling, u32 mask); | ||
20 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); | 27 | irqreturn_t mc_gp10b_isr_stall(struct gk20a *g); |
21 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); | 28 | irqreturn_t mc_gp10b_isr_nonstall(struct gk20a *g); |
22 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); | 29 | irqreturn_t mc_gp10b_intr_thread_stall(struct gk20a *g); |