diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu-t18x | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.c | 226 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/clk_gp106.h | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hw_trim_gp106.h | 189 |
5 files changed, 474 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x index c6b6f0d2..cd4ce5ce 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x +++ b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x | |||
@@ -38,7 +38,8 @@ nvgpu-y += \ | |||
38 | $(nvgpu-t18x)/perf/vfe_var.o \ | 38 | $(nvgpu-t18x)/perf/vfe_var.o \ |
39 | $(nvgpu-t18x)/perf/vfe_equ.o \ | 39 | $(nvgpu-t18x)/perf/vfe_equ.o \ |
40 | $(nvgpu-t18x)/perf/perf.o \ | 40 | $(nvgpu-t18x)/perf/perf.o \ |
41 | $(nvgpu-t18x)/clk/clk.o | 41 | $(nvgpu-t18x)/clk/clk.o \ |
42 | $(nvgpu-t18x)/gp106/clk_gp106.o | ||
42 | 43 | ||
43 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o | 44 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o |
44 | 45 | ||
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.c b/drivers/gpu/nvgpu/gp106/clk_gp106.c new file mode 100644 index 00000000..4bf03661 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.c | |||
@@ -0,0 +1,226 @@ | |||
1 | /* | ||
2 | * GP106 Clocks | ||
3 | * | ||
4 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License | ||
16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
17 | */ | ||
18 | |||
19 | #include <linux/clk.h> | ||
20 | #include <linux/delay.h> /* for mdelay */ | ||
21 | #include <linux/module.h> | ||
22 | #include <linux/debugfs.h> | ||
23 | #include <linux/uaccess.h> | ||
24 | #include <linux/clk/tegra.h> | ||
25 | #include <linux/tegra-fuse.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "hw_trim_gp106.h" | ||
29 | #include "clk_gp106.h" | ||
30 | |||
31 | #define gk20a_dbg_clk(fmt, arg...) \ | ||
32 | gk20a_dbg(gpu_dbg_clk, fmt, ##arg) | ||
33 | |||
34 | #ifdef CONFIG_DEBUG_FS | ||
35 | static int clk_gp106_debugfs_init(struct gk20a *g); | ||
36 | #endif | ||
37 | |||
38 | #define NUM_NAMEMAPS 4 | ||
39 | |||
40 | static int gp106_init_clk_support(struct gk20a *g) { | ||
41 | struct clk_gk20a *clk = &g->clk; | ||
42 | u32 err = 0; | ||
43 | |||
44 | gk20a_dbg_fn(""); | ||
45 | |||
46 | mutex_init(&clk->clk_mutex); | ||
47 | |||
48 | clk->clk_namemap = (struct namemap_cfg *) | ||
49 | kzalloc(sizeof(struct namemap_cfg) * NUM_NAMEMAPS, GFP_KERNEL); | ||
50 | |||
51 | if (!clk->clk_namemap) | ||
52 | return -ENOMEM; | ||
53 | |||
54 | clk->clk_namemap[0] = (struct namemap_cfg) { | ||
55 | .namemap = CLK_NAMEMAP_INDEX_GPC2CLK, | ||
56 | .is_enable = 1, | ||
57 | .is_counter = 1, | ||
58 | .g = g, | ||
59 | .cntr.reg_ctrl_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(), | ||
60 | .cntr.reg_ctrl_idx = | ||
61 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(), | ||
62 | .cntr.reg_cntr_addr = trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(), | ||
63 | .name = "gpc2clk" | ||
64 | }; | ||
65 | clk->clk_namemap[1] = (struct namemap_cfg) { | ||
66 | .namemap = CLK_NAMEMAP_INDEX_SYS2CLK, | ||
67 | .is_enable = 1, | ||
68 | .is_counter = 1, | ||
69 | .g = g, | ||
70 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncsyspll_cfg_r(), | ||
71 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(), | ||
72 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncsyspll_cnt_r(), | ||
73 | .name = "sys2clk" | ||
74 | }; | ||
75 | clk->clk_namemap[2] = (struct namemap_cfg) { | ||
76 | .namemap = CLK_NAMEMAP_INDEX_XBAR2CLK, | ||
77 | .is_enable = 1, | ||
78 | .is_counter = 1, | ||
79 | .g = g, | ||
80 | .cntr.reg_ctrl_addr = trim_sys_clk_cntr_ncltcpll_cfg_r(), | ||
81 | .cntr.reg_ctrl_idx = trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(), | ||
82 | .cntr.reg_cntr_addr = trim_sys_clk_cntr_ncltcpll_cnt_r(), | ||
83 | .name = "xbar2clk" | ||
84 | }; | ||
85 | clk->clk_namemap[3] = (struct namemap_cfg) { | ||
86 | .namemap = CLK_NAMEMAP_INDEX_DRAMCLK, | ||
87 | .is_enable = 1, | ||
88 | .is_counter = 1, | ||
89 | .g = g, | ||
90 | .cntr.reg_ctrl_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(), | ||
91 | .cntr.reg_ctrl_idx = | ||
92 | trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(), | ||
93 | .cntr.reg_cntr_addr = trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(), | ||
94 | .name = "dramdiv2_rec_clk1" | ||
95 | }; | ||
96 | |||
97 | clk->namemap_num = NUM_NAMEMAPS; | ||
98 | |||
99 | clk->g = g; | ||
100 | |||
101 | #ifdef CONFIG_DEBUG_FS | ||
102 | if (!clk->debugfs_set) { | ||
103 | if (!clk_gp106_debugfs_init(g)) | ||
104 | clk->debugfs_set = true; | ||
105 | } | ||
106 | #endif | ||
107 | return err; | ||
108 | } | ||
109 | |||
110 | #ifdef CONFIG_DEBUG_FS | ||
111 | typedef struct namemap_cfg namemap_cfg_t; | ||
112 | static u32 gp106_get_rate_cntr(struct gk20a *, struct namemap_cfg *); | ||
113 | |||
114 | static u32 gp106_get_rate_cntr(struct gk20a *g, struct namemap_cfg *c) { | ||
115 | u32 save_reg; | ||
116 | u32 retries; | ||
117 | u32 cntr = 0; | ||
118 | |||
119 | struct clk_gk20a *clk = &g->clk; | ||
120 | |||
121 | if (!c || !c->cntr.reg_ctrl_addr || !c->cntr.reg_cntr_addr) | ||
122 | return 0; | ||
123 | |||
124 | mutex_lock(&clk->clk_mutex); | ||
125 | |||
126 | /* Save the register */ | ||
127 | save_reg = gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
128 | |||
129 | /* Disable and reset the current clock */ | ||
130 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
131 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
132 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
133 | |||
134 | /* Force wb() */ | ||
135 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
136 | |||
137 | /* Wait for reset to happen */ | ||
138 | retries = CLK_DEFAULT_CNTRL_SETTLE_RETRIES; | ||
139 | do { | ||
140 | udelay(CLK_DEFAULT_CNTRL_SETTLE_USECS); | ||
141 | } while ((--retries) && (cntr = gk20a_readl(g, c->cntr.reg_cntr_addr))); | ||
142 | |||
143 | if (!retries) { | ||
144 | gk20a_err(dev_from_gk20a(g), | ||
145 | "unable to settle counter reset, bailing"); | ||
146 | goto read_err; | ||
147 | } | ||
148 | /* Program counter */ | ||
149 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
150 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f() | | ||
151 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f() | | ||
152 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
153 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
154 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f() | | ||
155 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(XTAL_CNTR_CLKS) | | ||
156 | c->cntr.reg_ctrl_idx); | ||
157 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
158 | |||
159 | udelay(XTAL_CNTR_DELAY); | ||
160 | |||
161 | cntr = XTAL_SCALE_TO_KHZ * gk20a_readl(g, c->cntr.reg_cntr_addr); | ||
162 | |||
163 | read_err: | ||
164 | /* reset and restore control register */ | ||
165 | gk20a_writel(g, c->cntr.reg_ctrl_addr, | ||
166 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f() | | ||
167 | trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f()); | ||
168 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
169 | gk20a_writel(g, c->cntr.reg_ctrl_addr, save_reg); | ||
170 | gk20a_readl(g, c->cntr.reg_ctrl_addr); | ||
171 | mutex_unlock(&clk->clk_mutex); | ||
172 | |||
173 | return cntr; | ||
174 | |||
175 | } | ||
176 | |||
177 | static int gp106_get_rate_show(void *data , u64 *val) { | ||
178 | struct namemap_cfg *c = (struct namemap_cfg *) data; | ||
179 | struct gk20a *g = c->g; | ||
180 | |||
181 | *val = c->is_counter ? gp106_get_rate_cntr(g, c) : 0 /* TODO PLL read */; | ||
182 | return 0; | ||
183 | } | ||
184 | DEFINE_SIMPLE_ATTRIBUTE(get_rate_fops, gp106_get_rate_show, NULL, "%llu\n"); | ||
185 | |||
186 | |||
187 | static int clk_gp106_debugfs_init(struct gk20a *g) { | ||
188 | struct gk20a_platform *platform = dev_get_drvdata(g->dev); | ||
189 | |||
190 | struct dentry *gpu_root = platform->debugfs; | ||
191 | struct dentry *clocks_root; | ||
192 | struct dentry *d; | ||
193 | int i; | ||
194 | |||
195 | if (NULL == (clocks_root = debugfs_create_dir("clocks", gpu_root))) | ||
196 | return -ENOMEM; | ||
197 | |||
198 | gk20a_dbg(gpu_dbg_info, "g=%p", g); | ||
199 | |||
200 | for (i = 0; i < g->clk.namemap_num; i++) { | ||
201 | if (g->clk.clk_namemap[i].is_enable) { | ||
202 | d = debugfs_create_file( | ||
203 | g->clk.clk_namemap[i].name, | ||
204 | S_IRUGO, | ||
205 | clocks_root, | ||
206 | &g->clk.clk_namemap[i], | ||
207 | &get_rate_fops); | ||
208 | if (!d) | ||
209 | goto err_out; | ||
210 | } | ||
211 | } | ||
212 | return 0; | ||
213 | |||
214 | err_out: | ||
215 | pr_err("%s: Failed to make debugfs node\n", __func__); | ||
216 | debugfs_remove_recursive(clocks_root); | ||
217 | return -ENOMEM; | ||
218 | } | ||
219 | |||
220 | #endif /* CONFIG_DEBUG_FS */ | ||
221 | |||
222 | void gp106_init_clk_ops(struct gpu_ops *gops) { | ||
223 | gops->clk.init_clk_support = gp106_init_clk_support; | ||
224 | } | ||
225 | |||
226 | |||
diff --git a/drivers/gpu/nvgpu/gp106/clk_gp106.h b/drivers/gpu/nvgpu/gp106/clk_gp106.h new file mode 100644 index 00000000..a50819aa --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/clk_gp106.h | |||
@@ -0,0 +1,55 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | #ifndef CLK_GP106_H | ||
17 | #define CLK_GP106_H | ||
18 | |||
19 | #include <linux/mutex.h> | ||
20 | |||
21 | #define CLK_NAMEMAP_INDEX_GPC2CLK 0x00 | ||
22 | #define CLK_NAMEMAP_INDEX_XBAR2CLK 0x02 | ||
23 | #define CLK_NAMEMAP_INDEX_SYS2CLK 0x07 /* SYSPLL */ | ||
24 | #define CLK_NAMEMAP_INDEX_DRAMCLK 0x20 /* DRAMPLL */ | ||
25 | |||
26 | #define CLK_DEFAULT_CNTRL_SETTLE_RETRIES 10 | ||
27 | #define CLK_DEFAULT_CNTRL_SETTLE_USECS 5 | ||
28 | |||
29 | #define XTAL_CNTR_CLKS 2700 /* 100usec at 27KHz XTAL */ | ||
30 | #define XTAL_CNTR_DELAY 110 /* leave 10 extra usec */ | ||
31 | #define XTAL_SCALE_TO_KHZ 10 | ||
32 | |||
33 | |||
34 | |||
35 | struct namemap_cfg { | ||
36 | u32 namemap; | ||
37 | u32 is_enable; /* Namemap enabled */ | ||
38 | u32 is_counter; /* Using cntr */ | ||
39 | struct gk20a *g; | ||
40 | union { | ||
41 | struct { | ||
42 | u32 reg_ctrl_addr; | ||
43 | u32 reg_ctrl_idx; | ||
44 | u32 reg_cntr_addr; | ||
45 | } cntr; | ||
46 | struct { | ||
47 | /* Todo */ | ||
48 | } pll; | ||
49 | }; | ||
50 | char name[24]; | ||
51 | }; | ||
52 | |||
53 | void gp106_init_clk_ops(struct gpu_ops *gops); | ||
54 | |||
55 | #endif /* CLK_GP106_H */ | ||
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 822591ed..6c8ac7bc 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -37,7 +37,7 @@ | |||
37 | #include "gm20b/gr_gm20b.h" | 37 | #include "gm20b/gr_gm20b.h" |
38 | #include "gm20b/fifo_gm20b.h" | 38 | #include "gm20b/fifo_gm20b.h" |
39 | #include "gm20b/pmu_gm20b.h" | 39 | #include "gm20b/pmu_gm20b.h" |
40 | #include "gm20b/clk_gm20b.h" | 40 | #include "gp106/clk_gp106.h" |
41 | 41 | ||
42 | #include "gp106/mm_gp106.h" | 42 | #include "gp106/mm_gp106.h" |
43 | #include "gp106/pmu_gp106.h" | 43 | #include "gp106/pmu_gp106.h" |
@@ -156,6 +156,7 @@ int gp106_init_hal(struct gk20a *g) | |||
156 | gp106_init_pmu_ops(gops); | 156 | gp106_init_pmu_ops(gops); |
157 | gk20a_init_debug_ops(gops); | 157 | gk20a_init_debug_ops(gops); |
158 | gk20a_init_dbg_session_ops(gops); | 158 | gk20a_init_dbg_session_ops(gops); |
159 | gp106_init_clk_ops(gops); | ||
159 | gp10b_init_regops(gops); | 160 | gp10b_init_regops(gops); |
160 | gp10b_init_cde_ops(gops); | 161 | gp10b_init_cde_ops(gops); |
161 | gk20a_init_tsg_ops(gops); | 162 | gk20a_init_tsg_ops(gops); |
diff --git a/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h b/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h new file mode 100644 index 00000000..42d3fd32 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/hw_trim_gp106.h | |||
@@ -0,0 +1,189 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | /* | ||
17 | * Function naming determines intended use: | ||
18 | * | ||
19 | * <x>_r(void) : Returns the offset for register <x>. | ||
20 | * | ||
21 | * <x>_o(void) : Returns the offset for element <x>. | ||
22 | * | ||
23 | * <x>_w(void) : Returns the word offset for word (4 byte) element <x>. | ||
24 | * | ||
25 | * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits. | ||
26 | * | ||
27 | * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted | ||
28 | * and masked to place it at field <y> of register <x>. This value | ||
29 | * can be |'d with others to produce a full register value for | ||
30 | * register <x>. | ||
31 | * | ||
32 | * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This | ||
33 | * value can be ~'d and then &'d to clear the value of field <y> for | ||
34 | * register <x>. | ||
35 | * | ||
36 | * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted | ||
37 | * to place it at field <y> of register <x>. This value can be |'d | ||
38 | * with others to produce a full register value for <x>. | ||
39 | * | ||
40 | * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register | ||
41 | * <x> value 'r' after being shifted to place its LSB at bit 0. | ||
42 | * This value is suitable for direct comparison with other unshifted | ||
43 | * values appropriate for use in field <y> of register <x>. | ||
44 | * | ||
45 | * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for | ||
46 | * field <y> of register <x>. This value is suitable for direct | ||
47 | * comparison with unshifted values appropriate for use in field <y> | ||
48 | * of register <x>. | ||
49 | */ | ||
50 | #ifndef _hw_trim_gp106_h_ | ||
51 | #define _hw_trim_gp106_h_ | ||
52 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_r(void) | ||
53 | { | ||
54 | return 0x00132924; | ||
55 | } | ||
56 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_s(void) | ||
57 | { | ||
58 | return 16; | ||
59 | } | ||
60 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v) | ||
61 | { | ||
62 | return (v & 0xffff) << 0; | ||
63 | } | ||
64 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_m(void) | ||
65 | { | ||
66 | return 0xffff << 0; | ||
67 | } | ||
68 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_noofipclks_v(u32 r) | ||
69 | { | ||
70 | return (r >> 0) & 0xffff; | ||
71 | } | ||
72 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_s(void) | ||
73 | { | ||
74 | return 1; | ||
75 | } | ||
76 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_f(u32 v) | ||
77 | { | ||
78 | return (v & 0x1) << 16; | ||
79 | } | ||
80 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_m(void) | ||
81 | { | ||
82 | return 0x1 << 16; | ||
83 | } | ||
84 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_v(u32 r) | ||
85 | { | ||
86 | return (r >> 16) & 0x1; | ||
87 | } | ||
88 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_deasserted_f(void) | ||
89 | { | ||
90 | return 0; | ||
91 | } | ||
92 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void) | ||
93 | { | ||
94 | return 0x10000; | ||
95 | } | ||
96 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_s(void) | ||
97 | { | ||
98 | return 1; | ||
99 | } | ||
100 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_f(u32 v) | ||
101 | { | ||
102 | return (v & 0x1) << 20; | ||
103 | } | ||
104 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_m(void) | ||
105 | { | ||
106 | return 0x1 << 20; | ||
107 | } | ||
108 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_v(u32 r) | ||
109 | { | ||
110 | return (r >> 20) & 0x1; | ||
111 | } | ||
112 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_deasserted_f(void) | ||
113 | { | ||
114 | return 0; | ||
115 | } | ||
116 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void) | ||
117 | { | ||
118 | return 0x100000; | ||
119 | } | ||
120 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_s(void) | ||
121 | { | ||
122 | return 1; | ||
123 | } | ||
124 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_f(u32 v) | ||
125 | { | ||
126 | return (v & 0x1) << 24; | ||
127 | } | ||
128 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_m(void) | ||
129 | { | ||
130 | return 0x1 << 24; | ||
131 | } | ||
132 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_v(u32 r) | ||
133 | { | ||
134 | return (r >> 24) & 0x1; | ||
135 | } | ||
136 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_deasserted_f(void) | ||
137 | { | ||
138 | return 0; | ||
139 | } | ||
140 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void) | ||
141 | { | ||
142 | return 0x1000000; | ||
143 | } | ||
144 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cfg_source_gpc2clk_f(void) | ||
145 | { | ||
146 | return 0x70000000; | ||
147 | } | ||
148 | static inline u32 trim_gpc_bcast_clk_cntr_ncgpcclk_cnt_r(void) | ||
149 | { | ||
150 | return 0x00132928; | ||
151 | } | ||
152 | static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_r(void) | ||
153 | { | ||
154 | return 0x00132128; | ||
155 | } | ||
156 | static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cfg_source_dramdiv4_rec_clk1_f(void) | ||
157 | { | ||
158 | return 0x20000000; | ||
159 | } | ||
160 | static inline u32 trim_fbpa_bcast_clk_cntr_ncltcclk_cnt_r(void) | ||
161 | { | ||
162 | return 0x0013212c; | ||
163 | } | ||
164 | static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_r(void) | ||
165 | { | ||
166 | return 0x001373c0; | ||
167 | } | ||
168 | static inline u32 trim_sys_clk_cntr_ncltcpll_cfg_source_xbar2clk_f(void) | ||
169 | { | ||
170 | return 0x20000000; | ||
171 | } | ||
172 | static inline u32 trim_sys_clk_cntr_ncltcpll_cnt_r(void) | ||
173 | { | ||
174 | return 0x001373c4; | ||
175 | } | ||
176 | static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_r(void) | ||
177 | { | ||
178 | return 0x001373b0; | ||
179 | } | ||
180 | static inline u32 trim_sys_clk_cntr_ncsyspll_cfg_source_sys2clk_f(void) | ||
181 | { | ||
182 | return 0x0; | ||
183 | } | ||
184 | static inline u32 trim_sys_clk_cntr_ncsyspll_cnt_r(void) | ||
185 | { | ||
186 | return 0x001373b4; | ||
187 | } | ||
188 | |||
189 | #endif | ||