diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 22 |
2 files changed, 20 insertions, 17 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index c766fc46..9f5ea39e 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -25,8 +25,8 @@ enum { | |||
25 | }; | 25 | }; |
26 | 26 | ||
27 | enum gpc_pll_mode { | 27 | enum gpc_pll_mode { |
28 | GPC_PLL_MODE_F = 0, | 28 | GPC_PLL_MODE_F = 0, /* fixed frequency mode a.k.a legacy mode */ |
29 | GPC_PLL_MODE_DVFS, | 29 | GPC_PLL_MODE_DVFS, /* DVFS mode a.k.a NA mode */ |
30 | }; | 30 | }; |
31 | 31 | ||
32 | struct na_dvfs { | 32 | struct na_dvfs { |
@@ -62,6 +62,16 @@ struct pll_parms { | |||
62 | int coeff_slope, coeff_offs; /* coeff = slope * V + offs */ | 62 | int coeff_slope, coeff_offs; /* coeff = slope * V + offs */ |
63 | int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */ | 63 | int uvdet_slope, uvdet_offs; /* uV = slope * det + offs */ |
64 | u32 vco_ctrl; | 64 | u32 vco_ctrl; |
65 | /* | ||
66 | * Timing parameters in us. Lock timeout is applied to locking in fixed | ||
67 | * frequency mode and to dynamic ramp in any mode; does not affect lock | ||
68 | * latency, since lock/ramp done status bit is polled. NA mode lock and | ||
69 | * and IDDQ exit delays set the time of the respective opertaions with | ||
70 | * no status polling. | ||
71 | */ | ||
72 | u32 lock_timeout; | ||
73 | u32 na_lock_delay; | ||
74 | u32 iddq_exit_delay; | ||
65 | }; | 75 | }; |
66 | 76 | ||
67 | struct clk_gk20a { | 77 | struct clk_gk20a { |
@@ -70,7 +80,6 @@ struct clk_gk20a { | |||
70 | struct pll gpc_pll; | 80 | struct pll gpc_pll; |
71 | struct pll gpc_pll_last; | 81 | struct pll gpc_pll_last; |
72 | u32 pll_delay; /* default PLL settle time */ | 82 | u32 pll_delay; /* default PLL settle time */ |
73 | u32 na_pll_delay; /* default PLL settle time in NA mode */ | ||
74 | struct mutex clk_mutex; | 83 | struct mutex clk_mutex; |
75 | bool sw_ready; | 84 | bool sw_ready; |
76 | bool clk_hw_on; | 85 | bool clk_hw_on; |
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d0a39bc6..16f929a8 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -56,6 +56,9 @@ static struct pll_parms gpc_pll_params = { | |||
56 | -165230, 214007, /* DFS_COEFF */ | 56 | -165230, 214007, /* DFS_COEFF */ |
57 | 0, 0, /* ADC char coeff - to be read from fuses */ | 57 | 0, 0, /* ADC char coeff - to be read from fuses */ |
58 | 0x7 << 3, /* vco control in NA mode */ | 58 | 0x7 << 3, /* vco control in NA mode */ |
59 | 500, /* Locking and ramping timeout */ | ||
60 | 40, /* Lock delay in NA mode */ | ||
61 | 5, /* IDDQ mode exit delay */ | ||
59 | }; | 62 | }; |
60 | 63 | ||
61 | #ifdef CONFIG_DEBUG_FS | 64 | #ifdef CONFIG_DEBUG_FS |
@@ -411,7 +414,7 @@ static void clk_setup_dvfs_detection(struct gk20a *g, struct pll *gpll) | |||
411 | static int clk_enbale_pll_dvfs(struct gk20a *g) | 414 | static int clk_enbale_pll_dvfs(struct gk20a *g) |
412 | { | 415 | { |
413 | u32 data; | 416 | u32 data; |
414 | int delay = 5; /* use for iddq exit delay & calib timeout */ | 417 | int delay = gpc_pll_params.iddq_exit_delay; /* iddq & calib delay */ |
415 | struct pll_parms *p = &gpc_pll_params; | 418 | struct pll_parms *p = &gpc_pll_params; |
416 | bool calibrated = p->uvdet_slope && p->uvdet_offs; | 419 | bool calibrated = p->uvdet_slope && p->uvdet_offs; |
417 | 420 | ||
@@ -527,7 +530,7 @@ static int clk_slide_gpc_pll(struct gk20a *g, struct pll *gpll) | |||
527 | { | 530 | { |
528 | u32 data, coeff; | 531 | u32 data, coeff; |
529 | u32 nold, sdm_old; | 532 | u32 nold, sdm_old; |
530 | int ramp_timeout = 500; | 533 | int ramp_timeout = gpc_pll_params.lock_timeout; |
531 | 534 | ||
532 | /* get old coefficients */ | 535 | /* get old coefficients */ |
533 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); | 536 | coeff = gk20a_readl(g, trim_sys_gpcpll_coeff_r()); |
@@ -666,7 +669,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) | |||
666 | trim_sys_gpcpll_cfg_iddq_power_on_v()); | 669 | trim_sys_gpcpll_cfg_iddq_power_on_v()); |
667 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); | 670 | gk20a_writel(g, trim_sys_gpcpll_cfg_r(), cfg); |
668 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 671 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
669 | udelay(5); | 672 | udelay(gpc_pll_params.iddq_exit_delay); |
670 | } else { | 673 | } else { |
671 | /* clear SYNC_MODE before disabling PLL */ | 674 | /* clear SYNC_MODE before disabling PLL */ |
672 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(), | 675 | cfg = set_field(cfg, trim_sys_gpcpll_cfg_sync_mode_m(), |
@@ -710,7 +713,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) | |||
710 | /* just delay in DVFS mode (lock cannot be used) */ | 713 | /* just delay in DVFS mode (lock cannot be used) */ |
711 | if (gpll->mode == GPC_PLL_MODE_DVFS) { | 714 | if (gpll->mode == GPC_PLL_MODE_DVFS) { |
712 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 715 | gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
713 | udelay(g->clk.na_pll_delay); | 716 | udelay(gpc_pll_params.na_lock_delay); |
714 | gk20a_dbg_clk("NA config_pll under bypass: %u (%u) kHz %d mV", | 717 | gk20a_dbg_clk("NA config_pll under bypass: %u (%u) kHz %d mV", |
715 | gpll->freq, gpll->freq / 2, | 718 | gpll->freq, gpll->freq / 2, |
716 | (trim_sys_gpcpll_cfg3_dfs_testout_v( | 719 | (trim_sys_gpcpll_cfg3_dfs_testout_v( |
@@ -730,7 +733,7 @@ static int clk_lock_gpc_pll_under_bypass(struct gk20a *g, struct pll *gpll) | |||
730 | } | 733 | } |
731 | 734 | ||
732 | /* wait pll lock */ | 735 | /* wait pll lock */ |
733 | timeout = g->clk.pll_delay + 1; | 736 | timeout = gpc_pll_params.lock_timeout + 1; |
734 | do { | 737 | do { |
735 | udelay(1); | 738 | udelay(1); |
736 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 739 | cfg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
@@ -1088,15 +1091,6 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1088 | return -EINVAL; | 1091 | return -EINVAL; |
1089 | } | 1092 | } |
1090 | 1093 | ||
1091 | /* | ||
1092 | * Locking time in both legacy and DVFS mode is 40us. However, in legacy | ||
1093 | * mode we rely on lock detection signal, and delay is just timeout | ||
1094 | * limit, so we can afford set it longer. In DVFS mode each lock inserts | ||
1095 | * specified delay, so it should be set as short as h/w allows. | ||
1096 | */ | ||
1097 | clk->pll_delay = 300; /* usec */ | ||
1098 | clk->na_pll_delay = 40; /* usec*/ | ||
1099 | |||
1100 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1094 | clk->gpc_pll.id = GK20A_GPC_PLL; |
1101 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; | 1095 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; |
1102 | 1096 | ||