diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 23 |
13 files changed, 42 insertions, 75 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 43ee8d7c..885ce172 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -367,7 +367,6 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
367 | if(tsg->sm_error_states != NULL) { | 367 | if(tsg->sm_error_states != NULL) { |
368 | nvgpu_kfree(g, tsg->sm_error_states); | 368 | nvgpu_kfree(g, tsg->sm_error_states); |
369 | tsg->sm_error_states = NULL; | 369 | tsg->sm_error_states = NULL; |
370 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
371 | } | 370 | } |
372 | 371 | ||
373 | /* unhook all events created on this TSG */ | 372 | /* unhook all events created on this TSG */ |
@@ -408,11 +407,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
408 | int err = 0; | 407 | int err = 0; |
409 | 408 | ||
410 | if (tsg->sm_error_states != NULL) { | 409 | if (tsg->sm_error_states != NULL) { |
411 | return -EINVAL; | ||
412 | } | ||
413 | |||
414 | err = nvgpu_mutex_init(&tsg->sm_exception_mask_lock); | ||
415 | if (err) { | ||
416 | return err; | 410 | return err; |
417 | } | 411 | } |
418 | 412 | ||
@@ -421,7 +415,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
421 | * num_sm); | 415 | * num_sm); |
422 | if (tsg->sm_error_states == NULL) { | 416 | if (tsg->sm_error_states == NULL) { |
423 | nvgpu_err(g, "sm_error_states mem allocation failed"); | 417 | nvgpu_err(g, "sm_error_states mem allocation failed"); |
424 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
425 | err = -ENOMEM; | 418 | err = -ENOMEM; |
426 | } | 419 | } |
427 | 420 | ||
@@ -447,20 +440,3 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
447 | tsg_sm_error_states->hww_warp_esr_report_mask = | 440 | tsg_sm_error_states->hww_warp_esr_report_mask = |
448 | sm_error_state->hww_warp_esr_report_mask; | 441 | sm_error_state->hww_warp_esr_report_mask; |
449 | } | 442 | } |
450 | |||
451 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
452 | u32 exception_mask) | ||
453 | { | ||
454 | struct tsg_gk20a *tsg; | ||
455 | |||
456 | tsg = tsg_gk20a_from_ch(ch); | ||
457 | if (!tsg) { | ||
458 | return -EINVAL; | ||
459 | } | ||
460 | |||
461 | nvgpu_mutex_acquire(&tsg->sm_exception_mask_lock); | ||
462 | tsg->sm_exception_mask_type = exception_mask; | ||
463 | nvgpu_mutex_release(&tsg->sm_exception_mask_lock); | ||
464 | |||
465 | return 0; | ||
466 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index d13cd388..1e3be553 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -82,7 +82,6 @@ struct tsg_gk20a { | |||
82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) | 82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) |
83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) | 83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) |
84 | u32 sm_exception_mask_type; | 84 | u32 sm_exception_mask_type; |
85 | struct nvgpu_mutex sm_exception_mask_lock; | ||
86 | }; | 85 | }; |
87 | 86 | ||
88 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); | 87 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); |
@@ -104,8 +103,6 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
104 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | 103 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, |
105 | u32 sm_id, | 104 | u32 sm_id, |
106 | struct nvgpu_tsg_sm_error_state *sm_error_state); | 105 | struct nvgpu_tsg_sm_error_state *sm_error_state); |
107 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
108 | u32 exception_mask); | ||
109 | 106 | ||
110 | struct gk20a_event_id_data { | 107 | struct gk20a_event_id_data { |
111 | struct gk20a *g; | 108 | struct gk20a *g; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 620fbc59..114d259a 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -477,7 +477,6 @@ static const struct gpu_ops gm20b_ops = { | |||
477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
480 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
481 | }, | 480 | }, |
482 | .gr_ctx = { | 481 | .gr_ctx = { |
483 | .get_netlist_name = gr_gm20b_get_netlist_name, | 482 | .get_netlist_name = gr_gm20b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index f996e141..94669eb3 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -552,7 +552,6 @@ static const struct gpu_ops gp106_ops = { | |||
552 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 552 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
553 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 553 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
554 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 554 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
555 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
556 | }, | 555 | }, |
557 | .gr_ctx = { | 556 | .gr_ctx = { |
558 | .get_netlist_name = gr_gp106_get_netlist_name, | 557 | .get_netlist_name = gr_gp106_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 68b50bca..63ab04e9 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -649,7 +649,6 @@ static const struct gpu_ops gv100_ops = { | |||
649 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 649 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
650 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 650 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
651 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 651 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
652 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
653 | }, | 652 | }, |
654 | .gr_ctx = { | 653 | .gr_ctx = { |
655 | .get_netlist_name = gr_gv100_get_netlist_name, | 654 | .get_netlist_name = gr_gv100_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 410101dd..9444002b 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -612,7 +612,6 @@ static const struct gpu_ops gv11b_ops = { | |||
612 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 612 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
613 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 613 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
614 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 614 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
615 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
616 | }, | 615 | }, |
617 | .gr_ctx = { | 616 | .gr_ctx = { |
618 | .get_netlist_name = gr_gv11b_get_netlist_name, | 617 | .get_netlist_name = gr_gv11b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 244b6ed2..39ab455b 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -748,8 +748,6 @@ struct gpu_ops { | |||
748 | struct nvgpu_semaphore *s, u64 sema_va, | 748 | struct nvgpu_semaphore *s, u64 sema_va, |
749 | struct priv_cmd_entry *cmd, | 749 | struct priv_cmd_entry *cmd, |
750 | u32 off, bool acquire, bool wfi); | 750 | u32 off, bool acquire, bool wfi); |
751 | int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, | ||
752 | u32 exception_mask); | ||
753 | } fifo; | 751 | } fifo; |
754 | struct pmu_v { | 752 | struct pmu_v { |
755 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 753 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index 8ef5236c..f7a58c87 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -123,7 +123,6 @@ enum { | |||
123 | TEGRA_VGPU_CMD_RESUME = 83, | 123 | TEGRA_VGPU_CMD_RESUME = 83, |
124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, | 124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, |
125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, | 125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, |
126 | TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86, | ||
127 | }; | 126 | }; |
128 | 127 | ||
129 | struct tegra_vgpu_connect_params { | 128 | struct tegra_vgpu_connect_params { |
@@ -468,11 +467,6 @@ struct tegra_vgpu_gpu_clk_rate_params { | |||
468 | u32 rate; /* in kHz */ | 467 | u32 rate; /* in kHz */ |
469 | }; | 468 | }; |
470 | 469 | ||
471 | struct tegra_vgpu_set_sm_exception_type_mask_params { | ||
472 | u64 handle; | ||
473 | u32 mask; | ||
474 | }; | ||
475 | |||
476 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | 470 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ |
477 | #define TEGRA_VGPU_MAX_ENGINES 4 | 471 | #define TEGRA_VGPU_MAX_ENGINES 4 |
478 | struct tegra_vgpu_engines_info { | 472 | struct tegra_vgpu_engines_info { |
@@ -684,7 +678,6 @@ struct tegra_vgpu_cmd_msg { | |||
684 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; | 678 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; |
685 | struct tegra_vgpu_ecc_info_params ecc_info; | 679 | struct tegra_vgpu_ecc_info_params ecc_info; |
686 | struct tegra_vgpu_ecc_counter_params ecc_counter; | 680 | struct tegra_vgpu_ecc_counter_params ecc_counter; |
687 | struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask; | ||
688 | char padding[192]; | 681 | char padding[192]; |
689 | } params; | 682 | } params; |
690 | }; | 683 | }; |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index fa33b6e0..953b7168 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -154,6 +154,10 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s); | |||
154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | 154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, |
155 | struct file *filp, bool is_profiler); | 155 | struct file *filp, bool is_profiler); |
156 | 156 | ||
157 | static int nvgpu_set_sm_exception_type_mask_locked( | ||
158 | struct dbg_session_gk20a *dbg_s, | ||
159 | u32 exception_mask); | ||
160 | |||
157 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) | 161 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) |
158 | { | 162 | { |
159 | unsigned int mask = 0; | 163 | unsigned int mask = 0; |
@@ -1804,13 +1808,44 @@ out: | |||
1804 | return err; | 1808 | return err; |
1805 | } | 1809 | } |
1806 | 1810 | ||
1807 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *dbg_s, | 1811 | static int nvgpu_set_sm_exception_type_mask_locked( |
1812 | struct dbg_session_gk20a *dbg_s, | ||
1813 | u32 exception_mask) | ||
1814 | { | ||
1815 | struct gk20a *g = dbg_s->g; | ||
1816 | int err = 0; | ||
1817 | struct channel_gk20a *ch = NULL; | ||
1818 | |||
1819 | /* | ||
1820 | * Obtain the fisrt channel from the channel list in | ||
1821 | * dbg_session, find the context associated with channel | ||
1822 | * and set the sm_mask_type to that context | ||
1823 | */ | ||
1824 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
1825 | if (ch != NULL) { | ||
1826 | struct tsg_gk20a *tsg; | ||
1827 | |||
1828 | tsg = tsg_gk20a_from_ch(ch); | ||
1829 | if (tsg != NULL) { | ||
1830 | tsg->sm_exception_mask_type = exception_mask; | ||
1831 | goto type_mask_end; | ||
1832 | } | ||
1833 | } | ||
1834 | |||
1835 | nvgpu_log_fn(g, "unable to find the TSG\n"); | ||
1836 | err = -EINVAL; | ||
1837 | |||
1838 | type_mask_end: | ||
1839 | return err; | ||
1840 | } | ||
1841 | |||
1842 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | ||
1843 | struct dbg_session_gk20a *dbg_s, | ||
1808 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) | 1844 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) |
1809 | { | 1845 | { |
1810 | int err = 0; | 1846 | int err = 0; |
1811 | struct gk20a *g = dbg_s->g; | 1847 | struct gk20a *g = dbg_s->g; |
1812 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | 1848 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; |
1813 | struct channel_gk20a *ch = NULL; | ||
1814 | 1849 | ||
1815 | switch (args->exception_type_mask) { | 1850 | switch (args->exception_type_mask) { |
1816 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1851 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: |
@@ -1831,13 +1866,10 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *db | |||
1831 | return err; | 1866 | return err; |
1832 | } | 1867 | } |
1833 | 1868 | ||
1834 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | 1869 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
1835 | if (ch != NULL) { | 1870 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, |
1836 | err = g->ops.fifo.set_sm_exception_type_mask(ch, | 1871 | sm_exception_mask_type); |
1837 | sm_exception_mask_type); | 1872 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
1838 | } else { | ||
1839 | err = -EINVAL; | ||
1840 | } | ||
1841 | 1873 | ||
1842 | return err; | 1874 | return err; |
1843 | } | 1875 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index ecaaaf23..20205d3c 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -61,5 +61,5 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
61 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); | 61 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); |
62 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | 62 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); |
63 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); | 63 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); |
64 | int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask); | 64 | |
65 | #endif | 65 | #endif |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 03839858..2ec08ae6 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -358,7 +358,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
358 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 358 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
359 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 359 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
360 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 360 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
361 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
362 | }, | 361 | }, |
363 | .gr_ctx = { | 362 | .gr_ctx = { |
364 | .get_netlist_name = gr_gp10b_get_netlist_name, | 363 | .get_netlist_name = gr_gp10b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index e3d042cf..eac57433 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -424,7 +424,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
424 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 424 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
425 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 425 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
426 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 426 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
427 | .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, | ||
428 | }, | 427 | }, |
429 | .gr_ctx = { | 428 | .gr_ctx = { |
430 | .get_netlist_name = gr_gv11b_get_netlist_name, | 429 | .get_netlist_name = gr_gv11b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index cd733f9d..a81b5022 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | |||
@@ -163,26 +163,3 @@ int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) | |||
163 | 163 | ||
164 | return err; | 164 | return err; |
165 | } | 165 | } |
166 | |||
167 | int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
168 | u32 exception_mask) | ||
169 | { | ||
170 | struct tegra_vgpu_cmd_msg msg; | ||
171 | struct tegra_vgpu_set_sm_exception_type_mask_params *p = | ||
172 | &msg.params.set_sm_exception_mask; | ||
173 | int err = 0; | ||
174 | struct gk20a *g = ch->g; | ||
175 | |||
176 | nvgpu_log_fn(g, " "); | ||
177 | |||
178 | msg.cmd = TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK; | ||
179 | msg.handle = vgpu_get_handle(g); | ||
180 | p->handle = ch->virt_ctx; | ||
181 | p->mask = exception_mask; | ||
182 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
183 | err = err ? err : msg.ret; | ||
184 | WARN_ON(err); | ||
185 | |||
186 | return err; | ||
187 | } | ||
188 | |||