diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | 46 |
2 files changed, 40 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 7bcf5281..abb53e66 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2021, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -8851,6 +8851,10 @@ int gr_gk20a_wait_for_pause(struct gk20a *g, struct nvgpu_warpstate *w_state) | |||
8851 | u32 gpc, tpc, sm, sm_id; | 8851 | u32 gpc, tpc, sm, sm_id; |
8852 | u32 global_mask; | 8852 | u32 global_mask; |
8853 | 8853 | ||
8854 | if (!g->ops.gr.get_sm_no_lock_down_hww_global_esr_mask || | ||
8855 | !g->ops.gr.lock_down_sm || !g->ops.gr.bpt_reg_info) | ||
8856 | return -EINVAL; | ||
8857 | |||
8854 | /* Wait for the SMs to reach full stop. This condition is: | 8858 | /* Wait for the SMs to reach full stop. This condition is: |
8855 | * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) | 8859 | * 1) All SMs with valid warps must be in the trap handler (SM_IN_TRAP_MODE) |
8856 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp | 8860 | * 2) All SMs in the trap handler must have equivalent VALID and PAUSED warp |
@@ -8908,6 +8912,9 @@ int gr_gk20a_clear_sm_errors(struct gk20a *g) | |||
8908 | u32 global_esr; | 8912 | u32 global_esr; |
8909 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); | 8913 | u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC); |
8910 | 8914 | ||
8915 | if (!g->ops.gr.get_sm_hww_global_esr || !g->ops.gr.clear_sm_hww) | ||
8916 | return -EINVAL; | ||
8917 | |||
8911 | for (gpc = 0; gpc < gr->gpc_count; gpc++) { | 8918 | for (gpc = 0; gpc < gr->gpc_count; gpc++) { |
8912 | 8919 | ||
8913 | /* check if any tpc has an exception */ | 8920 | /* check if any tpc has an exception */ |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c index ee141ff8..94162b4f 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2011-2020, NVIDIA Corporation. All rights reserved. | 2 | * Copyright (c) 2011-2021, NVIDIA Corporation. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -692,12 +692,15 @@ static int nvgpu_gpu_ioctl_trigger_suspend(struct gk20a *g) | |||
692 | 692 | ||
693 | err = gk20a_busy(g); | 693 | err = gk20a_busy(g); |
694 | if (err) | 694 | if (err) |
695 | return err; | 695 | return err; |
696 | 696 | ||
697 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 697 | if (g->ops.gr.trigger_suspend) { |
698 | err = gr_gk20a_elpg_protected_call(g, | 698 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
699 | err = gr_gk20a_elpg_protected_call(g, | ||
699 | g->ops.gr.trigger_suspend(g)); | 700 | g->ops.gr.trigger_suspend(g)); |
700 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 701 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
702 | } else | ||
703 | err = -EINVAL; | ||
701 | 704 | ||
702 | gk20a_idle(g); | 705 | gk20a_idle(g); |
703 | 706 | ||
@@ -731,8 +734,13 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | |||
731 | goto out_free; | 734 | goto out_free; |
732 | 735 | ||
733 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 736 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
734 | (void)gr_gk20a_elpg_protected_call(g, | 737 | if (g->ops.gr.wait_for_pause) { |
738 | (void)gr_gk20a_elpg_protected_call(g, | ||
735 | g->ops.gr.wait_for_pause(g, w_state)); | 739 | g->ops.gr.wait_for_pause(g, w_state)); |
740 | } else { | ||
741 | err = -EINVAL; | ||
742 | goto out_idle; | ||
743 | } | ||
736 | 744 | ||
737 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { | 745 | for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) { |
738 | ioctl_w_state[sm_id].valid_warps[0] = | 746 | ioctl_w_state[sm_id].valid_warps[0] = |
@@ -755,6 +763,7 @@ static int nvgpu_gpu_ioctl_wait_for_pause(struct gk20a *g, | |||
755 | err = -EFAULT; | 763 | err = -EFAULT; |
756 | } | 764 | } |
757 | 765 | ||
766 | out_idle: | ||
758 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 767 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
759 | 768 | ||
760 | gk20a_idle(g); | 769 | gk20a_idle(g); |
@@ -772,12 +781,15 @@ static int nvgpu_gpu_ioctl_resume_from_pause(struct gk20a *g) | |||
772 | 781 | ||
773 | err = gk20a_busy(g); | 782 | err = gk20a_busy(g); |
774 | if (err) | 783 | if (err) |
775 | return err; | 784 | return err; |
776 | 785 | ||
777 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 786 | if (g->ops.gr.resume_from_pause) { |
778 | err = gr_gk20a_elpg_protected_call(g, | 787 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
788 | err = gr_gk20a_elpg_protected_call(g, | ||
779 | g->ops.gr.resume_from_pause(g)); | 789 | g->ops.gr.resume_from_pause(g)); |
780 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 790 | nvgpu_mutex_release(&g->dbg_sessions_lock); |
791 | } else | ||
792 | err = -EINVAL; | ||
781 | 793 | ||
782 | gk20a_idle(g); | 794 | gk20a_idle(g); |
783 | 795 | ||
@@ -792,8 +804,11 @@ static int nvgpu_gpu_ioctl_clear_sm_errors(struct gk20a *g) | |||
792 | if (err) | 804 | if (err) |
793 | return err; | 805 | return err; |
794 | 806 | ||
795 | err = gr_gk20a_elpg_protected_call(g, | 807 | if (g->ops.gr.clear_sm_errors) { |
808 | err = gr_gk20a_elpg_protected_call(g, | ||
796 | g->ops.gr.clear_sm_errors(g)); | 809 | g->ops.gr.clear_sm_errors(g)); |
810 | } else | ||
811 | err = -EINVAL; | ||
797 | 812 | ||
798 | gk20a_idle(g); | 813 | gk20a_idle(g); |
799 | 814 | ||
@@ -806,9 +821,12 @@ static int nvgpu_gpu_ioctl_has_any_exception( | |||
806 | { | 821 | { |
807 | u32 tpc_exception_en; | 822 | u32 tpc_exception_en; |
808 | 823 | ||
809 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 824 | if (g->ops.gr.tpc_enabled_exceptions) { |
810 | tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g); | 825 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); |
811 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 826 | tpc_exception_en = g->ops.gr.tpc_enabled_exceptions(g); |
827 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
828 | } else | ||
829 | return -EINVAL; | ||
812 | 830 | ||
813 | args->tpc_exception_en_sm_mask = tpc_exception_en; | 831 | args->tpc_exception_en_sm_mask = tpc_exception_en; |
814 | 832 | ||