diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | 16 |
2 files changed, 43 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index e783f8d0..c12ab1f6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -4995,14 +4995,21 @@ static int gk20a_gr_handle_fecs_error(struct gk20a *g, | |||
4995 | { | 4995 | { |
4996 | struct fifo_gk20a *f = &g->fifo; | 4996 | struct fifo_gk20a *f = &g->fifo; |
4997 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; | 4997 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; |
4998 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_intr_r()); | 4998 | u32 gr_fecs_intr = gk20a_readl(g, gr_fecs_host_int_status_r()); |
4999 | gk20a_dbg_fn(""); | 4999 | gk20a_dbg_fn(""); |
5000 | 5000 | ||
5001 | gk20a_err(dev_from_gk20a(g), | 5001 | gk20a_err(dev_from_gk20a(g), |
5002 | "unhandled fecs error interrupt 0x%08x for channel %u", | 5002 | "unhandled fecs error interrupt 0x%08x for channel %u", |
5003 | gr_fecs_intr, ch->hw_chid); | 5003 | gr_fecs_intr, ch->hw_chid); |
5004 | 5004 | ||
5005 | gk20a_writel(g, gr_fecs_intr_r(), gr_fecs_intr); | 5005 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { |
5006 | gk20a_err(dev_from_gk20a(g), | ||
5007 | "firmware method error 0x%08x for offset 0x%04x", | ||
5008 | gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(6)), | ||
5009 | isr_data->data_lo); | ||
5010 | } | ||
5011 | |||
5012 | gk20a_writel(g, gr_fecs_host_int_clear_r(), gr_fecs_intr); | ||
5006 | return -EINVAL; | 5013 | return -EINVAL; |
5007 | } | 5014 | } |
5008 | 5015 | ||
@@ -5024,6 +5031,23 @@ static int gk20a_gr_handle_class_error(struct gk20a *g, | |||
5024 | return -EINVAL; | 5031 | return -EINVAL; |
5025 | } | 5032 | } |
5026 | 5033 | ||
5034 | static int gk20a_gr_handle_firmware_method(struct gk20a *g, | ||
5035 | struct gr_isr_data *isr_data) | ||
5036 | { | ||
5037 | struct fifo_gk20a *f = &g->fifo; | ||
5038 | struct channel_gk20a *ch = &f->channel[isr_data->chid]; | ||
5039 | |||
5040 | gk20a_dbg_fn(""); | ||
5041 | |||
5042 | gk20a_set_error_notifier(ch, | ||
5043 | NVHOST_CHANNEL_GR_ERROR_SW_NOTIFY); | ||
5044 | gk20a_err(dev_from_gk20a(g), | ||
5045 | "firmware method 0x%08x, offset 0x%08x for channel %u\n", | ||
5046 | isr_data->class_num, isr_data->offset, | ||
5047 | ch->hw_chid); | ||
5048 | return -EINVAL; | ||
5049 | } | ||
5050 | |||
5027 | static int gk20a_gr_handle_semaphore_pending(struct gk20a *g, | 5051 | static int gk20a_gr_handle_semaphore_pending(struct gk20a *g, |
5028 | struct gr_isr_data *isr_data) | 5052 | struct gr_isr_data *isr_data) |
5029 | { | 5053 | { |
@@ -5513,7 +5537,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
5513 | /* this one happens if someone tries to hit a non-whitelisted | 5537 | /* this one happens if someone tries to hit a non-whitelisted |
5514 | * register using set_falcon[4] */ | 5538 | * register using set_falcon[4] */ |
5515 | if (gr_intr & gr_intr_firmware_method_pending_f()) { | 5539 | if (gr_intr & gr_intr_firmware_method_pending_f()) { |
5516 | need_reset |= true; | 5540 | need_reset |= gk20a_gr_handle_firmware_method(g, &isr_data); |
5517 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "firmware method intr pending\n"); | 5541 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "firmware method intr pending\n"); |
5518 | gk20a_writel(g, gr_intr_r(), | 5542 | gk20a_writel(g, gr_intr_r(), |
5519 | gr_intr_firmware_method_reset_f()); | 5543 | gr_intr_firmware_method_reset_f()); |
diff --git a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h index b670d9aa..9f1fb32b 100644 --- a/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/hw_gr_gk20a.h | |||
@@ -718,6 +718,22 @@ static inline u32 gr_fecs_method_push_adr_set_watchdog_timeout_f(void) | |||
718 | { | 718 | { |
719 | return 0x21; | 719 | return 0x21; |
720 | } | 720 | } |
721 | static inline u32 gr_fecs_host_int_status_r(void) | ||
722 | { | ||
723 | return 0x00409c18; | ||
724 | } | ||
725 | static inline u32 gr_fecs_host_int_status_umimp_firmware_method_f(u32 v) | ||
726 | { | ||
727 | return (v & 0x1) << 17; | ||
728 | } | ||
729 | static inline u32 gr_fecs_host_int_status_umimp_illegal_method_f(u32 v) | ||
730 | { | ||
731 | return (v & 0x1) << 18; | ||
732 | } | ||
733 | static inline u32 gr_fecs_host_int_clear_r(void) | ||
734 | { | ||
735 | return 0x00409c20; | ||
736 | } | ||
721 | static inline u32 gr_fecs_host_int_enable_r(void) | 737 | static inline u32 gr_fecs_host_int_enable_r(void) |
722 | { | 738 | { |
723 | return 0x00409c24; | 739 | return 0x00409c24; |