diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | 24 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | 23 |
13 files changed, 75 insertions, 42 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c index 885ce172..43ee8d7c 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.c | |||
@@ -367,6 +367,7 @@ void gk20a_tsg_release(struct nvgpu_ref *ref) | |||
367 | if(tsg->sm_error_states != NULL) { | 367 | if(tsg->sm_error_states != NULL) { |
368 | nvgpu_kfree(g, tsg->sm_error_states); | 368 | nvgpu_kfree(g, tsg->sm_error_states); |
369 | tsg->sm_error_states = NULL; | 369 | tsg->sm_error_states = NULL; |
370 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
370 | } | 371 | } |
371 | 372 | ||
372 | /* unhook all events created on this TSG */ | 373 | /* unhook all events created on this TSG */ |
@@ -407,6 +408,11 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
407 | int err = 0; | 408 | int err = 0; |
408 | 409 | ||
409 | if (tsg->sm_error_states != NULL) { | 410 | if (tsg->sm_error_states != NULL) { |
411 | return -EINVAL; | ||
412 | } | ||
413 | |||
414 | err = nvgpu_mutex_init(&tsg->sm_exception_mask_lock); | ||
415 | if (err) { | ||
410 | return err; | 416 | return err; |
411 | } | 417 | } |
412 | 418 | ||
@@ -415,6 +421,7 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
415 | * num_sm); | 421 | * num_sm); |
416 | if (tsg->sm_error_states == NULL) { | 422 | if (tsg->sm_error_states == NULL) { |
417 | nvgpu_err(g, "sm_error_states mem allocation failed"); | 423 | nvgpu_err(g, "sm_error_states mem allocation failed"); |
424 | nvgpu_mutex_destroy(&tsg->sm_exception_mask_lock); | ||
418 | err = -ENOMEM; | 425 | err = -ENOMEM; |
419 | } | 426 | } |
420 | 427 | ||
@@ -440,3 +447,20 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | |||
440 | tsg_sm_error_states->hww_warp_esr_report_mask = | 447 | tsg_sm_error_states->hww_warp_esr_report_mask = |
441 | sm_error_state->hww_warp_esr_report_mask; | 448 | sm_error_state->hww_warp_esr_report_mask; |
442 | } | 449 | } |
450 | |||
451 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
452 | u32 exception_mask) | ||
453 | { | ||
454 | struct tsg_gk20a *tsg; | ||
455 | |||
456 | tsg = tsg_gk20a_from_ch(ch); | ||
457 | if (!tsg) { | ||
458 | return -EINVAL; | ||
459 | } | ||
460 | |||
461 | nvgpu_mutex_acquire(&tsg->sm_exception_mask_lock); | ||
462 | tsg->sm_exception_mask_type = exception_mask; | ||
463 | nvgpu_mutex_release(&tsg->sm_exception_mask_lock); | ||
464 | |||
465 | return 0; | ||
466 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h index 1e3be553..d13cd388 100644 --- a/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/tsg_gk20a.h | |||
@@ -82,6 +82,7 @@ struct tsg_gk20a { | |||
82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) | 82 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_NONE (0x0U) |
83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) | 83 | #define NVGPU_SM_EXCEPTION_TYPE_MASK_FATAL (0x1U << 0) |
84 | u32 sm_exception_mask_type; | 84 | u32 sm_exception_mask_type; |
85 | struct nvgpu_mutex sm_exception_mask_lock; | ||
85 | }; | 86 | }; |
86 | 87 | ||
87 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); | 88 | int gk20a_enable_tsg(struct tsg_gk20a *tsg); |
@@ -103,6 +104,8 @@ int gk20a_tsg_alloc_sm_error_states_mem(struct gk20a *g, | |||
103 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, | 104 | void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg, |
104 | u32 sm_id, | 105 | u32 sm_id, |
105 | struct nvgpu_tsg_sm_error_state *sm_error_state); | 106 | struct nvgpu_tsg_sm_error_state *sm_error_state); |
107 | int gk20a_tsg_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
108 | u32 exception_mask); | ||
106 | 109 | ||
107 | struct gk20a_event_id_data { | 110 | struct gk20a_event_id_data { |
108 | struct gk20a *g; | 111 | struct gk20a *g; |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 114d259a..620fbc59 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -477,6 +477,7 @@ static const struct gpu_ops gm20b_ops = { | |||
477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 477 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 478 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 479 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
480 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
480 | }, | 481 | }, |
481 | .gr_ctx = { | 482 | .gr_ctx = { |
482 | .get_netlist_name = gr_gm20b_get_netlist_name, | 483 | .get_netlist_name = gr_gm20b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 94669eb3..f996e141 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -552,6 +552,7 @@ static const struct gpu_ops gp106_ops = { | |||
552 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 552 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
553 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 553 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
554 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 554 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
555 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
555 | }, | 556 | }, |
556 | .gr_ctx = { | 557 | .gr_ctx = { |
557 | .get_netlist_name = gr_gp106_get_netlist_name, | 558 | .get_netlist_name = gr_gp106_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 63ab04e9..68b50bca 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -649,6 +649,7 @@ static const struct gpu_ops gv100_ops = { | |||
649 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 649 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
650 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 650 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
651 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 651 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
652 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
652 | }, | 653 | }, |
653 | .gr_ctx = { | 654 | .gr_ctx = { |
654 | .get_netlist_name = gr_gv100_get_netlist_name, | 655 | .get_netlist_name = gr_gv100_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 9444002b..410101dd 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -612,6 +612,7 @@ static const struct gpu_ops gv11b_ops = { | |||
612 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 612 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
613 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 613 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
614 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 614 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
615 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
615 | }, | 616 | }, |
616 | .gr_ctx = { | 617 | .gr_ctx = { |
617 | .get_netlist_name = gr_gv11b_get_netlist_name, | 618 | .get_netlist_name = gr_gv11b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 9799425e..a653109a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -748,6 +748,8 @@ struct gpu_ops { | |||
748 | struct nvgpu_semaphore *s, u64 sema_va, | 748 | struct nvgpu_semaphore *s, u64 sema_va, |
749 | struct priv_cmd_entry *cmd, | 749 | struct priv_cmd_entry *cmd, |
750 | u32 off, bool acquire, bool wfi); | 750 | u32 off, bool acquire, bool wfi); |
751 | int (*set_sm_exception_type_mask)(struct channel_gk20a *ch, | ||
752 | u32 exception_mask); | ||
751 | } fifo; | 753 | } fifo; |
752 | struct pmu_v { | 754 | struct pmu_v { |
753 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); | 755 | u32 (*get_pmu_cmdline_args_size)(struct nvgpu_pmu *pmu); |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h index f7a58c87..8ef5236c 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/vgpu/tegra_vgpu.h | |||
@@ -123,6 +123,7 @@ enum { | |||
123 | TEGRA_VGPU_CMD_RESUME = 83, | 123 | TEGRA_VGPU_CMD_RESUME = 83, |
124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, | 124 | TEGRA_VGPU_CMD_GET_ECC_INFO = 84, |
125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, | 125 | TEGRA_VGPU_CMD_GET_ECC_COUNTER_VALUE = 85, |
126 | TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK = 86, | ||
126 | }; | 127 | }; |
127 | 128 | ||
128 | struct tegra_vgpu_connect_params { | 129 | struct tegra_vgpu_connect_params { |
@@ -467,6 +468,11 @@ struct tegra_vgpu_gpu_clk_rate_params { | |||
467 | u32 rate; /* in kHz */ | 468 | u32 rate; /* in kHz */ |
468 | }; | 469 | }; |
469 | 470 | ||
471 | struct tegra_vgpu_set_sm_exception_type_mask_params { | ||
472 | u64 handle; | ||
473 | u32 mask; | ||
474 | }; | ||
475 | |||
470 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ | 476 | /* TEGRA_VGPU_MAX_ENGINES must be equal or greater than num_engines */ |
471 | #define TEGRA_VGPU_MAX_ENGINES 4 | 477 | #define TEGRA_VGPU_MAX_ENGINES 4 |
472 | struct tegra_vgpu_engines_info { | 478 | struct tegra_vgpu_engines_info { |
@@ -678,6 +684,7 @@ struct tegra_vgpu_cmd_msg { | |||
678 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; | 684 | struct tegra_vgpu_channel_update_pc_sampling update_pc_sampling; |
679 | struct tegra_vgpu_ecc_info_params ecc_info; | 685 | struct tegra_vgpu_ecc_info_params ecc_info; |
680 | struct tegra_vgpu_ecc_counter_params ecc_counter; | 686 | struct tegra_vgpu_ecc_counter_params ecc_counter; |
687 | struct tegra_vgpu_set_sm_exception_type_mask_params set_sm_exception_mask; | ||
681 | char padding[192]; | 688 | char padding[192]; |
682 | } params; | 689 | } params; |
683 | }; | 690 | }; |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 953b7168..fa33b6e0 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -154,10 +154,6 @@ static int dbg_unbind_all_channels_gk20a(struct dbg_session_gk20a *dbg_s); | |||
154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, | 154 | static int gk20a_dbg_gpu_do_dev_open(struct inode *inode, |
155 | struct file *filp, bool is_profiler); | 155 | struct file *filp, bool is_profiler); |
156 | 156 | ||
157 | static int nvgpu_set_sm_exception_type_mask_locked( | ||
158 | struct dbg_session_gk20a *dbg_s, | ||
159 | u32 exception_mask); | ||
160 | |||
161 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) | 157 | unsigned int gk20a_dbg_gpu_dev_poll(struct file *filep, poll_table *wait) |
162 | { | 158 | { |
163 | unsigned int mask = 0; | 159 | unsigned int mask = 0; |
@@ -1808,44 +1804,13 @@ out: | |||
1808 | return err; | 1804 | return err; |
1809 | } | 1805 | } |
1810 | 1806 | ||
1811 | static int nvgpu_set_sm_exception_type_mask_locked( | 1807 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask(struct dbg_session_gk20a *dbg_s, |
1812 | struct dbg_session_gk20a *dbg_s, | ||
1813 | u32 exception_mask) | ||
1814 | { | ||
1815 | struct gk20a *g = dbg_s->g; | ||
1816 | int err = 0; | ||
1817 | struct channel_gk20a *ch = NULL; | ||
1818 | |||
1819 | /* | ||
1820 | * Obtain the fisrt channel from the channel list in | ||
1821 | * dbg_session, find the context associated with channel | ||
1822 | * and set the sm_mask_type to that context | ||
1823 | */ | ||
1824 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
1825 | if (ch != NULL) { | ||
1826 | struct tsg_gk20a *tsg; | ||
1827 | |||
1828 | tsg = tsg_gk20a_from_ch(ch); | ||
1829 | if (tsg != NULL) { | ||
1830 | tsg->sm_exception_mask_type = exception_mask; | ||
1831 | goto type_mask_end; | ||
1832 | } | ||
1833 | } | ||
1834 | |||
1835 | nvgpu_log_fn(g, "unable to find the TSG\n"); | ||
1836 | err = -EINVAL; | ||
1837 | |||
1838 | type_mask_end: | ||
1839 | return err; | ||
1840 | } | ||
1841 | |||
1842 | static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | ||
1843 | struct dbg_session_gk20a *dbg_s, | ||
1844 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) | 1808 | struct nvgpu_dbg_gpu_set_sm_exception_type_mask_args *args) |
1845 | { | 1809 | { |
1846 | int err = 0; | 1810 | int err = 0; |
1847 | struct gk20a *g = dbg_s->g; | 1811 | struct gk20a *g = dbg_s->g; |
1848 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; | 1812 | u32 sm_exception_mask_type = NVGPU_SM_EXCEPTION_TYPE_MASK_NONE; |
1813 | struct channel_gk20a *ch = NULL; | ||
1849 | 1814 | ||
1850 | switch (args->exception_type_mask) { | 1815 | switch (args->exception_type_mask) { |
1851 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: | 1816 | case NVGPU_DBG_GPU_IOCTL_SET_SM_EXCEPTION_TYPE_MASK_FATAL: |
@@ -1866,10 +1831,13 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask( | |||
1866 | return err; | 1831 | return err; |
1867 | } | 1832 | } |
1868 | 1833 | ||
1869 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | 1834 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); |
1870 | err = nvgpu_set_sm_exception_type_mask_locked(dbg_s, | 1835 | if (ch != NULL) { |
1871 | sm_exception_mask_type); | 1836 | err = g->ops.fifo.set_sm_exception_type_mask(ch, |
1872 | nvgpu_mutex_release(&g->dbg_sessions_lock); | 1837 | sm_exception_mask_type); |
1838 | } else { | ||
1839 | err = -EINVAL; | ||
1840 | } | ||
1873 | 1841 | ||
1874 | return err; | 1842 | return err; |
1875 | } | 1843 | } |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h index 20205d3c..ecaaaf23 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.h | |||
@@ -61,5 +61,5 @@ int vgpu_tsg_bind_channel(struct tsg_gk20a *tsg, | |||
61 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); | 61 | int vgpu_tsg_unbind_channel(struct channel_gk20a *ch); |
62 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); | 62 | int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice); |
63 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); | 63 | int vgpu_enable_tsg(struct tsg_gk20a *tsg); |
64 | 64 | int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, u32 mask); | |
65 | #endif | 65 | #endif |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 2ec08ae6..03839858 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -358,6 +358,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
358 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, | 358 | .get_sema_wait_cmd_size = gk20a_fifo_get_sema_wait_cmd_size, |
359 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, | 359 | .get_sema_incr_cmd_size = gk20a_fifo_get_sema_incr_cmd_size, |
360 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, | 360 | .add_sema_cmd = gk20a_fifo_add_sema_cmd, |
361 | .set_sm_exception_type_mask = gk20a_tsg_set_sm_exception_type_mask, | ||
361 | }, | 362 | }, |
362 | .gr_ctx = { | 363 | .gr_ctx = { |
363 | .get_netlist_name = gr_gp10b_get_netlist_name, | 364 | .get_netlist_name = gr_gp10b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index eac57433..e3d042cf 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -424,6 +424,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
424 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, | 424 | .get_sema_wait_cmd_size = gv11b_fifo_get_sema_wait_cmd_size, |
425 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, | 425 | .get_sema_incr_cmd_size = gv11b_fifo_get_sema_incr_cmd_size, |
426 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, | 426 | .add_sema_cmd = gv11b_fifo_add_sema_cmd, |
427 | .set_sm_exception_type_mask = vgpu_set_sm_exception_type_mask, | ||
427 | }, | 428 | }, |
428 | .gr_ctx = { | 429 | .gr_ctx = { |
429 | .get_netlist_name = gr_gv11b_get_netlist_name, | 430 | .get_netlist_name = gr_gv11b_get_netlist_name, |
diff --git a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c index a81b5022..cd733f9d 100644 --- a/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/tsg_vgpu.c | |||
@@ -163,3 +163,26 @@ int vgpu_tsg_set_timeslice(struct tsg_gk20a *tsg, u32 timeslice) | |||
163 | 163 | ||
164 | return err; | 164 | return err; |
165 | } | 165 | } |
166 | |||
167 | int vgpu_set_sm_exception_type_mask(struct channel_gk20a *ch, | ||
168 | u32 exception_mask) | ||
169 | { | ||
170 | struct tegra_vgpu_cmd_msg msg; | ||
171 | struct tegra_vgpu_set_sm_exception_type_mask_params *p = | ||
172 | &msg.params.set_sm_exception_mask; | ||
173 | int err = 0; | ||
174 | struct gk20a *g = ch->g; | ||
175 | |||
176 | nvgpu_log_fn(g, " "); | ||
177 | |||
178 | msg.cmd = TEGRA_VGPU_CMD_SET_SM_EXCEPTION_TYPE_MASK; | ||
179 | msg.handle = vgpu_get_handle(g); | ||
180 | p->handle = ch->virt_ctx; | ||
181 | p->mask = exception_mask; | ||
182 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
183 | err = err ? err : msg.ret; | ||
184 | WARN_ON(err); | ||
185 | |||
186 | return err; | ||
187 | } | ||
188 | |||