diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_common.c | 62 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/clk_gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | 31 |
5 files changed, 34 insertions, 77 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index 8bb64af7..3045af60 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -139,7 +139,6 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
139 | 139 | ||
140 | nvgpu-$(CONFIG_COMMON_CLK) += \ | 140 | nvgpu-$(CONFIG_COMMON_CLK) += \ |
141 | tegra/linux/clk.o \ | 141 | tegra/linux/clk.o \ |
142 | clk/clk_common.o \ | ||
143 | gm20b/clk_gm20b.o | 142 | gm20b/clk_gm20b.o |
144 | 143 | ||
145 | nvgpu-$(CONFIG_GK20A_DEVFREQ) += \ | 144 | nvgpu-$(CONFIG_GK20A_DEVFREQ) += \ |
diff --git a/drivers/gpu/nvgpu/clk/clk_common.c b/drivers/gpu/nvgpu/clk/clk_common.c deleted file mode 100644 index 0704ba2b..00000000 --- a/drivers/gpu/nvgpu/clk/clk_common.c +++ /dev/null | |||
@@ -1,62 +0,0 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | * | ||
13 | * You should have received a copy of the GNU General Public License | ||
14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
15 | */ | ||
16 | |||
17 | #include <linux/clk.h> | ||
18 | |||
19 | #include "gk20a/gk20a.h" | ||
20 | #include "gk20a/platform_gk20a.h" | ||
21 | |||
22 | struct clk *gk20a_clk_get(struct gk20a *g) | ||
23 | { | ||
24 | if (!g->clk.tegra_clk) { | ||
25 | struct clk *clk; | ||
26 | char clk_dev_id[32]; | ||
27 | struct device *dev = dev_from_gk20a(g); | ||
28 | |||
29 | snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev)); | ||
30 | |||
31 | clk = clk_get_sys(clk_dev_id, "gpu"); | ||
32 | if (IS_ERR(clk)) { | ||
33 | nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n", | ||
34 | clk_dev_id); | ||
35 | return NULL; | ||
36 | } | ||
37 | g->clk.tegra_clk = clk; | ||
38 | } | ||
39 | |||
40 | return g->clk.tegra_clk; | ||
41 | } | ||
42 | |||
43 | unsigned long gk20a_clk_get_rate(struct gk20a *g) | ||
44 | { | ||
45 | struct clk_gk20a *clk = &g->clk; | ||
46 | return rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
47 | } | ||
48 | |||
49 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate) | ||
50 | { | ||
51 | /* make sure the clock is available */ | ||
52 | if (!gk20a_clk_get(g)) | ||
53 | return rate; | ||
54 | |||
55 | return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate); | ||
56 | } | ||
57 | |||
58 | int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate) | ||
59 | { | ||
60 | return clk_set_rate(g->clk.tegra_clk, rate); | ||
61 | } | ||
62 | |||
diff --git a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h index 76f5de43..65f82263 100644 --- a/drivers/gpu/nvgpu/gk20a/clk_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/clk_gk20a.h | |||
@@ -105,12 +105,6 @@ struct clk_gk20a { | |||
105 | 105 | ||
106 | struct gpu_ops; | 106 | struct gpu_ops; |
107 | 107 | ||
108 | /* APIs used for both GK20A and GM20B */ | ||
109 | unsigned long gk20a_clk_get_rate(struct gk20a *g); | ||
110 | int gk20a_clk_set_rate(struct gk20a *g, unsigned long rate); | ||
111 | long gk20a_clk_round_rate(struct gk20a *g, unsigned long rate); | ||
112 | struct clk *gk20a_clk_get(struct gk20a *g); | ||
113 | |||
114 | #define KHZ 1000 | 108 | #define KHZ 1000 |
115 | #define MHZ 1000000 | 109 | #define MHZ 1000000 |
116 | 110 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index c4e65767..3d90938d 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1147,11 +1147,6 @@ int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1147 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; | 1147 | clk->pll_poweron_uv = BOOT_GPU_UV_B1; |
1148 | } | 1148 | } |
1149 | 1149 | ||
1150 | if (!gk20a_clk_get(g)) { | ||
1151 | err = -EINVAL; | ||
1152 | goto fail; | ||
1153 | } | ||
1154 | |||
1155 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; | 1150 | clk->gpc_pll.clk_in = g->ops.clk.get_ref_clock_rate(g) / KHZ; |
1156 | if (clk->gpc_pll.clk_in == 0) { | 1151 | if (clk->gpc_pll.clk_in == 0) { |
1157 | nvgpu_err(g, "GPCPLL reference clock is zero"); | 1152 | nvgpu_err(g, "GPCPLL reference clock is zero"); |
@@ -1451,13 +1446,15 @@ void gm20b_init_clk_ops(struct gpu_ops *gops) | |||
1451 | static int rate_get(void *data, u64 *val) | 1446 | static int rate_get(void *data, u64 *val) |
1452 | { | 1447 | { |
1453 | struct gk20a *g = (struct gk20a *)data; | 1448 | struct gk20a *g = (struct gk20a *)data; |
1454 | *val = (u64)gk20a_clk_get_rate(g); | 1449 | struct clk_gk20a *clk = &g->clk; |
1450 | |||
1451 | *val = (u64)rate_gpc2clk_to_gpu(clk->gpc_pll.freq); | ||
1455 | return 0; | 1452 | return 0; |
1456 | } | 1453 | } |
1457 | static int rate_set(void *data, u64 val) | 1454 | static int rate_set(void *data, u64 val) |
1458 | { | 1455 | { |
1459 | struct gk20a *g = (struct gk20a *)data; | 1456 | struct gk20a *g = (struct gk20a *)data; |
1460 | return gk20a_clk_set_rate(g, (u32)val); | 1457 | return g->ops.clk.set_rate(g, CTRL_CLK_DOMAIN_GPCCLK, (u32)val); |
1461 | } | 1458 | } |
1462 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); | 1459 | DEFINE_SIMPLE_ATTRIBUTE(rate_fops, rate_get, rate_set, "%llu\n"); |
1463 | 1460 | ||
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c index d6e448d8..a3b73cdf 100644 --- a/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c +++ b/drivers/gpu/nvgpu/tegra/linux/platform_gk20a_tegra.c | |||
@@ -754,6 +754,27 @@ void gk20a_tegra_init_secure_alloc(struct gk20a *g) | |||
754 | } | 754 | } |
755 | 755 | ||
756 | #ifdef CONFIG_COMMON_CLK | 756 | #ifdef CONFIG_COMMON_CLK |
757 | static struct clk *gk20a_clk_get(struct gk20a *g) | ||
758 | { | ||
759 | if (!g->clk.tegra_clk) { | ||
760 | struct clk *clk; | ||
761 | char clk_dev_id[32]; | ||
762 | struct device *dev = dev_from_gk20a(g); | ||
763 | |||
764 | snprintf(clk_dev_id, 32, "tegra_%s", dev_name(dev)); | ||
765 | |||
766 | clk = clk_get_sys(clk_dev_id, "gpu"); | ||
767 | if (IS_ERR(clk)) { | ||
768 | nvgpu_err(g, "fail to get tegra gpu clk %s/gpu\n", | ||
769 | clk_dev_id); | ||
770 | return NULL; | ||
771 | } | ||
772 | g->clk.tegra_clk = clk; | ||
773 | } | ||
774 | |||
775 | return g->clk.tegra_clk; | ||
776 | } | ||
777 | |||
757 | static int gm20b_clk_prepare_ops(struct clk_hw *hw) | 778 | static int gm20b_clk_prepare_ops(struct clk_hw *hw) |
758 | { | 779 | { |
759 | struct clk_gk20a *clk = to_clk_gk20a(hw); | 780 | struct clk_gk20a *clk = to_clk_gk20a(hw); |
@@ -809,6 +830,10 @@ static int gm20b_register_gpcclk(struct gk20a *g) | |||
809 | struct clk *c; | 830 | struct clk *c; |
810 | int err = 0; | 831 | int err = 0; |
811 | 832 | ||
833 | /* make sure the clock is available */ | ||
834 | if (!gk20a_clk_get(g)) | ||
835 | return -ENOSYS; | ||
836 | |||
812 | err = gm20b_init_clk_setup_sw(g); | 837 | err = gm20b_init_clk_setup_sw(g); |
813 | if (err) | 838 | if (err) |
814 | return err; | 839 | return err; |
@@ -958,7 +983,11 @@ static long gk20a_round_clk_rate(struct device *dev, unsigned long rate) | |||
958 | struct gk20a_platform *platform = gk20a_get_platform(dev); | 983 | struct gk20a_platform *platform = gk20a_get_platform(dev); |
959 | struct gk20a *g = platform->g; | 984 | struct gk20a *g = platform->g; |
960 | 985 | ||
961 | return gk20a_clk_round_rate(g, rate); | 986 | /* make sure the clock is available */ |
987 | if (!gk20a_clk_get(g)) | ||
988 | return rate; | ||
989 | |||
990 | return clk_round_rate(clk_get_parent(g->clk.tegra_clk), rate); | ||
962 | } | 991 | } |
963 | 992 | ||
964 | static int gk20a_clk_get_freqs(struct device *dev, | 993 | static int gk20a_clk_get_freqs(struct device *dev, |