diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 47 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h | 6 |
6 files changed, 69 insertions, 21 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index c7cd1d73..ac3a3d57 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1165,29 +1165,12 @@ static const char * const does_not_exist[] = { | |||
1165 | "does not exist" | 1165 | "does not exist" |
1166 | }; | 1166 | }; |
1167 | 1167 | ||
1168 | /* reads info from hardware and fills in mmu fault info record */ | 1168 | static void get_exception_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, |
1169 | static void get_exception_mmu_fault_info( | ||
1170 | struct gk20a *g, u32 mmu_fault_id, | ||
1171 | struct mmu_fault_info *mmfault) | 1169 | struct mmu_fault_info *mmfault) |
1172 | { | 1170 | { |
1173 | u32 fault_info; | 1171 | g->ops.fifo.get_mmu_fault_info(g, mmu_fault_id, mmfault); |
1174 | u32 addr_lo, addr_hi; | ||
1175 | |||
1176 | gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); | ||
1177 | |||
1178 | memset(mmfault, 0, sizeof(*mmfault)); | ||
1179 | |||
1180 | fault_info = gk20a_readl(g, | ||
1181 | fifo_intr_mmu_fault_info_r(mmu_fault_id)); | ||
1182 | mmfault->fault_type = | ||
1183 | fifo_intr_mmu_fault_info_type_v(fault_info); | ||
1184 | mmfault->access_type = | ||
1185 | fifo_intr_mmu_fault_info_write_v(fault_info); | ||
1186 | mmfault->client_type = | ||
1187 | fifo_intr_mmu_fault_info_engine_subid_v(fault_info); | ||
1188 | mmfault->client_id = | ||
1189 | fifo_intr_mmu_fault_info_client_v(fault_info); | ||
1190 | 1172 | ||
1173 | /* parse info */ | ||
1191 | if (mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)) { | 1174 | if (mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)) { |
1192 | WARN_ON(mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)); | 1175 | WARN_ON(mmfault->fault_type >= ARRAY_SIZE(fault_type_descs)); |
1193 | mmfault->fault_type_desc = does_not_exist[0]; | 1176 | mmfault->fault_type_desc = does_not_exist[0]; |
@@ -1224,6 +1207,29 @@ static void get_exception_mmu_fault_info( | |||
1224 | mmfault->client_id_desc = | 1207 | mmfault->client_id_desc = |
1225 | gpc_client_descs[mmfault->client_id]; | 1208 | gpc_client_descs[mmfault->client_id]; |
1226 | } | 1209 | } |
1210 | } | ||
1211 | |||
1212 | /* reads info from hardware and fills in mmu fault info record */ | ||
1213 | void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | ||
1214 | struct mmu_fault_info *mmfault) | ||
1215 | { | ||
1216 | u32 fault_info; | ||
1217 | u32 addr_lo, addr_hi; | ||
1218 | |||
1219 | gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); | ||
1220 | |||
1221 | memset(mmfault, 0, sizeof(*mmfault)); | ||
1222 | |||
1223 | fault_info = gk20a_readl(g, | ||
1224 | fifo_intr_mmu_fault_info_r(mmu_fault_id)); | ||
1225 | mmfault->fault_type = | ||
1226 | fifo_intr_mmu_fault_info_type_v(fault_info); | ||
1227 | mmfault->access_type = | ||
1228 | fifo_intr_mmu_fault_info_write_v(fault_info); | ||
1229 | mmfault->client_type = | ||
1230 | fifo_intr_mmu_fault_info_engine_subid_v(fault_info); | ||
1231 | mmfault->client_id = | ||
1232 | fifo_intr_mmu_fault_info_client_v(fault_info); | ||
1227 | 1233 | ||
1228 | addr_lo = gk20a_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id)); | 1234 | addr_lo = gk20a_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id)); |
1229 | addr_hi = gk20a_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id)); | 1235 | addr_hi = gk20a_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id)); |
@@ -4381,6 +4387,7 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
4381 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; | 4387 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; |
4382 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | 4388 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; |
4383 | gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; | 4389 | gops->fifo.trigger_mmu_fault = gk20a_fifo_trigger_mmu_fault; |
4390 | gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; | ||
4384 | gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; | 4391 | gops->fifo.apply_pb_timeout = gk20a_fifo_apply_pb_timeout; |
4385 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | 4392 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; |
4386 | gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; | 4393 | gops->fifo.get_num_fifos = gk20a_fifo_get_num_fifos; |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 55075f3b..6c8868a2 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -406,4 +406,6 @@ int gk20a_fifo_alloc_syncpt_buf(struct channel_gk20a *c, | |||
406 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); | 406 | u32 syncpt_id, struct nvgpu_mem *syncpt_buf); |
407 | #endif | 407 | #endif |
408 | 408 | ||
409 | void gk20a_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | ||
410 | struct mmu_fault_info *mmfault); | ||
409 | #endif /*__GR_GK20A_H__*/ | 411 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 1dff07fa..10417084 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -439,6 +439,8 @@ struct gpu_ops { | |||
439 | bool wait_for_finish); | 439 | bool wait_for_finish); |
440 | void (*trigger_mmu_fault)(struct gk20a *g, | 440 | void (*trigger_mmu_fault)(struct gk20a *g, |
441 | unsigned long engine_ids); | 441 | unsigned long engine_ids); |
442 | void (*get_mmu_fault_info)(struct gk20a *g, u32 mmu_fault_id, | ||
443 | struct mmu_fault_info *mmfault); | ||
442 | void (*apply_pb_timeout)(struct gk20a *g); | 444 | void (*apply_pb_timeout)(struct gk20a *g); |
443 | int (*wait_engine_idle)(struct gk20a *g); | 445 | int (*wait_engine_idle)(struct gk20a *g); |
444 | u32 (*get_num_fifos)(struct gk20a *g); | 446 | u32 (*get_num_fifos)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 6fb5802b..df3015da 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -206,6 +206,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
206 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; | 206 | gops->fifo.preempt_tsg = gk20a_fifo_preempt_tsg; |
207 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | 207 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; |
208 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; | 208 | gops->fifo.trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault; |
209 | gops->fifo.get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info; | ||
209 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; | 210 | gops->fifo.wait_engine_idle = gk20a_fifo_wait_engine_idle; |
210 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; | 211 | gops->fifo.get_num_fifos = gm20b_fifo_get_num_fifos; |
211 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; | 212 | gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; |
diff --git a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c index 59e127b7..386318e7 100644 --- a/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/fifo_gp10b.c | |||
@@ -277,9 +277,41 @@ static void gp10b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f) | |||
277 | pbdma_intr_0_device_pending_f(); | 277 | pbdma_intr_0_device_pending_f(); |
278 | } | 278 | } |
279 | 279 | ||
280 | static void gp10b_fifo_get_mmu_fault_info(struct gk20a *g, u32 mmu_fault_id, | ||
281 | struct mmu_fault_info *mmfault) | ||
282 | { | ||
283 | u32 fault_info; | ||
284 | u32 addr_lo, addr_hi; | ||
285 | |||
286 | gk20a_dbg_fn("mmu_fault_id %d", mmu_fault_id); | ||
287 | |||
288 | memset(mmfault, 0, sizeof(*mmfault)); | ||
289 | |||
290 | fault_info = gk20a_readl(g, | ||
291 | fifo_intr_mmu_fault_info_r(mmu_fault_id)); | ||
292 | mmfault->fault_type = | ||
293 | fifo_intr_mmu_fault_info_type_v(fault_info); | ||
294 | mmfault->access_type = | ||
295 | fifo_intr_mmu_fault_info_access_type_v(fault_info); | ||
296 | mmfault->client_type = | ||
297 | fifo_intr_mmu_fault_info_client_type_v(fault_info); | ||
298 | mmfault->client_id = | ||
299 | fifo_intr_mmu_fault_info_client_v(fault_info); | ||
300 | |||
301 | addr_lo = gk20a_readl(g, fifo_intr_mmu_fault_lo_r(mmu_fault_id)); | ||
302 | addr_hi = gk20a_readl(g, fifo_intr_mmu_fault_hi_r(mmu_fault_id)); | ||
303 | mmfault->fault_addr = hi32_lo32_to_u64(addr_hi, addr_lo); | ||
304 | /* note:ignoring aperture */ | ||
305 | mmfault->inst_ptr = fifo_intr_mmu_fault_inst_ptr_v( | ||
306 | gk20a_readl(g, fifo_intr_mmu_fault_inst_r(mmu_fault_id))); | ||
307 | /* note: inst_ptr is a 40b phys addr. */ | ||
308 | mmfault->inst_ptr <<= fifo_intr_mmu_fault_inst_ptr_align_shift_v(); | ||
309 | } | ||
310 | |||
280 | void gp10b_init_fifo(struct gpu_ops *gops) | 311 | void gp10b_init_fifo(struct gpu_ops *gops) |
281 | { | 312 | { |
282 | gm20b_init_fifo(gops); | 313 | gm20b_init_fifo(gops); |
314 | gops->fifo.get_mmu_fault_info = gp10b_fifo_get_mmu_fault_info; | ||
283 | gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; | 315 | gops->fifo.setup_ramfc = channel_gp10b_setup_ramfc; |
284 | gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; | 316 | gops->fifo.get_pbdma_signature = gp10b_fifo_get_pbdma_signature; |
285 | gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; | 317 | gops->fifo.resetup_ramfc = gp10b_fifo_resetup_ramfc; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h index 8370d4c6..541b4dd4 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gp10b/hw_fifo_gp10b.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * This program is free software; you can redistribute it and/or modify it | 4 | * This program is free software; you can redistribute it and/or modify it |
5 | * under the terms and conditions of the GNU General Public License, | 5 | * under the terms and conditions of the GNU General Public License, |
@@ -302,6 +302,10 @@ static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) | |||
302 | { | 302 | { |
303 | return (r >> 0) & 0x1f; | 303 | return (r >> 0) & 0x1f; |
304 | } | 304 | } |
305 | static inline u32 fifo_intr_mmu_fault_info_access_type_v(u32 r) | ||
306 | { | ||
307 | return (r >> 16) & 0x7; | ||
308 | } | ||
305 | static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) | 309 | static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) |
306 | { | 310 | { |
307 | return (r >> 20) & 0x1; | 311 | return (r >> 20) & 0x1; |