diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 36 |
1 files changed, 20 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 61d3b6f5..0f7d5cde 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -28,6 +28,8 @@ | |||
28 | #include <nvgpu/soc.h> | 28 | #include <nvgpu/soc.h> |
29 | #include <nvgpu/fuse.h> | 29 | #include <nvgpu/fuse.h> |
30 | #include <nvgpu/bug.h> | 30 | #include <nvgpu/bug.h> |
31 | #include <nvgpu/log.h> | ||
32 | #include <nvgpu/types.h> | ||
31 | 33 | ||
32 | #include <nvgpu/hw/gm20b/hw_trim_gm20b.h> | 34 | #include <nvgpu/hw/gm20b/hw_trim_gm20b.h> |
33 | #include <nvgpu/hw/gm20b/hw_timer_gm20b.h> | 35 | #include <nvgpu/hw/gm20b/hw_timer_gm20b.h> |
@@ -84,24 +86,26 @@ static struct pll_parms gpc_pll_params; | |||
84 | 86 | ||
85 | static void clk_setup_slide(struct gk20a *g, u32 clk_u); | 87 | static void clk_setup_slide(struct gk20a *g, u32 clk_u); |
86 | 88 | ||
87 | #define DUMP_REG(addr_func) \ | ||
88 | do { \ | ||
89 | addr = trim_sys_##addr_func##_r(); \ | ||
90 | data = gk20a_readl(g, addr); \ | ||
91 | pr_info(#addr_func "[0x%x] = 0x%x\n", addr, data); \ | ||
92 | } while (0) | ||
93 | |||
94 | static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg) | 89 | static void dump_gpc_pll(struct gk20a *g, struct pll *gpll, u32 last_cfg) |
95 | { | 90 | { |
96 | u32 addr, data; | 91 | #define __DUMP_REG(__addr_str__) \ |
97 | 92 | do { \ | |
98 | pr_info("**** GPCPLL DUMP ****"); | 93 | u32 __addr__ = trim_sys_ ## __addr_str__ ## _r(); \ |
99 | pr_info("gpcpll s/w M=%u N=%u P=%u\n", gpll->M, gpll->N, gpll->PL); | 94 | u32 __data__ = gk20a_readl(g, __addr__); \ |
100 | pr_info("gpcpll_cfg_last = 0x%x\n", last_cfg); | 95 | \ |
101 | DUMP_REG(gpcpll_cfg); | 96 | nvgpu_info(g, " " #__addr_str__ " [0x%x] = 0x%x", \ |
102 | DUMP_REG(gpcpll_coeff); | 97 | __addr__, __data__); \ |
103 | DUMP_REG(sel_vco); | 98 | } while (0) |
104 | pr_info("\n"); | 99 | |
100 | nvgpu_info(g, "GPCPLL DUMP:"); | ||
101 | nvgpu_info(g, " gpcpll s/w M=%u N=%u P=%u\n", gpll->M, gpll->N, gpll->PL); | ||
102 | nvgpu_info(g, " gpcpll_cfg_last = 0x%x\n", last_cfg); | ||
103 | |||
104 | __DUMP_REG(gpcpll_cfg); | ||
105 | __DUMP_REG(gpcpll_coeff); | ||
106 | __DUMP_REG(sel_vco); | ||
107 | |||
108 | #undef __DUMP_REG | ||
105 | } | 109 | } |
106 | 110 | ||
107 | #define PLDIV_GLITCHLESS 1 | 111 | #define PLDIV_GLITCHLESS 1 |