diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/log.h | 56 |
1 files changed, 27 insertions, 29 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h index 7d7a41e3..183948cd 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/log.h +++ b/drivers/gpu/nvgpu/include/nvgpu/log.h | |||
@@ -53,35 +53,33 @@ void __nvgpu_log_dbg(struct gk20a *g, u32 log_mask, | |||
53 | */ | 53 | */ |
54 | #define NVGPU_DEFAULT_DBG_MASK (0) | 54 | #define NVGPU_DEFAULT_DBG_MASK (0) |
55 | 55 | ||
56 | enum nvgpu_log_categories { | 56 | #define gpu_dbg_info BIT(0) /* Lightly verbose info. */ |
57 | gpu_dbg_info = BIT(0), /* Lightly verbose info. */ | 57 | #define gpu_dbg_fn BIT(1) /* Function name tracing. */ |
58 | gpu_dbg_fn = BIT(1), /* Function name tracing. */ | 58 | #define gpu_dbg_reg BIT(2) /* Register accesses; very verbose. */ |
59 | gpu_dbg_reg = BIT(2), /* Register accesses; very verbose. */ | 59 | #define gpu_dbg_pte BIT(3) /* GMMU PTEs. */ |
60 | gpu_dbg_pte = BIT(3), /* GMMU PTEs. */ | 60 | #define gpu_dbg_intr BIT(4) /* Interrupts. */ |
61 | gpu_dbg_intr = BIT(4), /* Interrupts. */ | 61 | #define gpu_dbg_pmu BIT(5) /* gk20a pmu. */ |
62 | gpu_dbg_pmu = BIT(5), /* gk20a pmu. */ | 62 | #define gpu_dbg_clk BIT(6) /* gk20a clk. */ |
63 | gpu_dbg_clk = BIT(6), /* gk20a clk. */ | 63 | #define gpu_dbg_map BIT(7) /* Memory mappings. */ |
64 | gpu_dbg_map = BIT(7), /* Memory mappings. */ | 64 | #define gpu_dbg_map_v BIT(8) /* Verbose mem mappings. */ |
65 | gpu_dbg_map_v = BIT(8), /* Verbose mem mappings. */ | 65 | #define gpu_dbg_gpu_dbg BIT(9) /* GPU debugger/profiler. */ |
66 | gpu_dbg_gpu_dbg = BIT(9), /* GPU debugger/profiler. */ | 66 | #define gpu_dbg_cde BIT(10) /* cde info messages. */ |
67 | gpu_dbg_cde = BIT(10), /* cde info messages. */ | 67 | #define gpu_dbg_cde_ctx BIT(11) /* cde context usage messages. */ |
68 | gpu_dbg_cde_ctx = BIT(11), /* cde context usage messages. */ | 68 | #define gpu_dbg_ctxsw BIT(12) /* ctxsw tracing. */ |
69 | gpu_dbg_ctxsw = BIT(12), /* ctxsw tracing. */ | 69 | #define gpu_dbg_sched BIT(13) /* Sched control tracing. */ |
70 | gpu_dbg_sched = BIT(13), /* Sched control tracing. */ | 70 | #define gpu_dbg_sema BIT(14) /* Semaphore debugging. */ |
71 | gpu_dbg_sema = BIT(14), /* Semaphore debugging. */ | 71 | #define gpu_dbg_sema_v BIT(15) /* Verbose semaphore debugging. */ |
72 | gpu_dbg_sema_v = BIT(15), /* Verbose semaphore debugging. */ | 72 | #define gpu_dbg_pmu_pstate BIT(16) /* p state controlled by pmu. */ |
73 | gpu_dbg_pmu_pstate = BIT(16), /* p state controlled by pmu. */ | 73 | #define gpu_dbg_xv BIT(17) /* XVE debugging. */ |
74 | gpu_dbg_xv = BIT(17), /* XVE debugging. */ | 74 | #define gpu_dbg_shutdown BIT(18) /* GPU shutdown tracing. */ |
75 | gpu_dbg_shutdown = BIT(18), /* GPU shutdown tracing. */ | 75 | #define gpu_dbg_kmem BIT(19) /* Kmem tracking debugging. */ |
76 | gpu_dbg_kmem = BIT(19), /* Kmem tracking debugging. */ | 76 | #define gpu_dbg_pd_cache BIT(20) /* PD cache traces. */ |
77 | gpu_dbg_pd_cache = BIT(20), /* PD cache traces. */ | 77 | #define gpu_dbg_alloc BIT(21) /* Allocator debugging. */ |
78 | gpu_dbg_alloc = BIT(21), /* Allocator debugging. */ | 78 | #define gpu_dbg_dma BIT(22) /* DMA allocation prints. */ |
79 | gpu_dbg_dma = BIT(22), /* DMA allocation prints. */ | 79 | #define gpu_dbg_sgl BIT(23) /* SGL related traces. */ |
80 | gpu_dbg_sgl = BIT(23), /* SGL related traces. */ | 80 | #define gpu_dbg_vidmem BIT(24) /* VIDMEM tracing. */ |
81 | gpu_dbg_vidmem = BIT(24), /* VIDMEM tracing. */ | 81 | #define gpu_dbg_nvlink BIT(25) /* nvlink Operation tracing. */ |
82 | gpu_dbg_nvlink = BIT(25), /* nvlink Operation tracing. */ | 82 | #define gpu_dbg_mem BIT(31) /* memory accesses; very verbose. */ |
83 | gpu_dbg_mem = BIT(31), /* memory accesses; very verbose. */ | ||
84 | }; | ||
85 | 83 | ||
86 | /** | 84 | /** |
87 | * nvgpu_log_mask_enabled - Check if logging is enabled | 85 | * nvgpu_log_mask_enabled - Check if logging is enabled |