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-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h557
1 files changed, 557 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h
new file mode 100644
index 00000000..6bdc5fd1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_falcon_gv11b.h
@@ -0,0 +1,557 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_falcon_gv11b_h_
51#define _hw_falcon_gv11b_h_
52
53static inline u32 falcon_falcon_irqsset_r(void)
54{
55 return 0x00000000;
56}
57static inline u32 falcon_falcon_irqsset_swgen0_set_f(void)
58{
59 return 0x40;
60}
61static inline u32 falcon_falcon_irqsclr_r(void)
62{
63 return 0x00000004;
64}
65static inline u32 falcon_falcon_irqstat_r(void)
66{
67 return 0x00000008;
68}
69static inline u32 falcon_falcon_irqstat_halt_true_f(void)
70{
71 return 0x10;
72}
73static inline u32 falcon_falcon_irqstat_exterr_true_f(void)
74{
75 return 0x20;
76}
77static inline u32 falcon_falcon_irqstat_swgen0_true_f(void)
78{
79 return 0x40;
80}
81static inline u32 falcon_falcon_irqmode_r(void)
82{
83 return 0x0000000c;
84}
85static inline u32 falcon_falcon_irqmset_r(void)
86{
87 return 0x00000010;
88}
89static inline u32 falcon_falcon_irqmset_gptmr_f(u32 v)
90{
91 return (v & 0x1) << 0;
92}
93static inline u32 falcon_falcon_irqmset_wdtmr_f(u32 v)
94{
95 return (v & 0x1) << 1;
96}
97static inline u32 falcon_falcon_irqmset_mthd_f(u32 v)
98{
99 return (v & 0x1) << 2;
100}
101static inline u32 falcon_falcon_irqmset_ctxsw_f(u32 v)
102{
103 return (v & 0x1) << 3;
104}
105static inline u32 falcon_falcon_irqmset_halt_f(u32 v)
106{
107 return (v & 0x1) << 4;
108}
109static inline u32 falcon_falcon_irqmset_exterr_f(u32 v)
110{
111 return (v & 0x1) << 5;
112}
113static inline u32 falcon_falcon_irqmset_swgen0_f(u32 v)
114{
115 return (v & 0x1) << 6;
116}
117static inline u32 falcon_falcon_irqmset_swgen1_f(u32 v)
118{
119 return (v & 0x1) << 7;
120}
121static inline u32 falcon_falcon_irqmclr_r(void)
122{
123 return 0x00000014;
124}
125static inline u32 falcon_falcon_irqmclr_gptmr_f(u32 v)
126{
127 return (v & 0x1) << 0;
128}
129static inline u32 falcon_falcon_irqmclr_wdtmr_f(u32 v)
130{
131 return (v & 0x1) << 1;
132}
133static inline u32 falcon_falcon_irqmclr_mthd_f(u32 v)
134{
135 return (v & 0x1) << 2;
136}
137static inline u32 falcon_falcon_irqmclr_ctxsw_f(u32 v)
138{
139 return (v & 0x1) << 3;
140}
141static inline u32 falcon_falcon_irqmclr_halt_f(u32 v)
142{
143 return (v & 0x1) << 4;
144}
145static inline u32 falcon_falcon_irqmclr_exterr_f(u32 v)
146{
147 return (v & 0x1) << 5;
148}
149static inline u32 falcon_falcon_irqmclr_swgen0_f(u32 v)
150{
151 return (v & 0x1) << 6;
152}
153static inline u32 falcon_falcon_irqmclr_swgen1_f(u32 v)
154{
155 return (v & 0x1) << 7;
156}
157static inline u32 falcon_falcon_irqmclr_ext_f(u32 v)
158{
159 return (v & 0xff) << 8;
160}
161static inline u32 falcon_falcon_irqmask_r(void)
162{
163 return 0x00000018;
164}
165static inline u32 falcon_falcon_irqdest_r(void)
166{
167 return 0x0000001c;
168}
169static inline u32 falcon_falcon_irqdest_host_gptmr_f(u32 v)
170{
171 return (v & 0x1) << 0;
172}
173static inline u32 falcon_falcon_irqdest_host_wdtmr_f(u32 v)
174{
175 return (v & 0x1) << 1;
176}
177static inline u32 falcon_falcon_irqdest_host_mthd_f(u32 v)
178{
179 return (v & 0x1) << 2;
180}
181static inline u32 falcon_falcon_irqdest_host_ctxsw_f(u32 v)
182{
183 return (v & 0x1) << 3;
184}
185static inline u32 falcon_falcon_irqdest_host_halt_f(u32 v)
186{
187 return (v & 0x1) << 4;
188}
189static inline u32 falcon_falcon_irqdest_host_exterr_f(u32 v)
190{
191 return (v & 0x1) << 5;
192}
193static inline u32 falcon_falcon_irqdest_host_swgen0_f(u32 v)
194{
195 return (v & 0x1) << 6;
196}
197static inline u32 falcon_falcon_irqdest_host_swgen1_f(u32 v)
198{
199 return (v & 0x1) << 7;
200}
201static inline u32 falcon_falcon_irqdest_host_ext_f(u32 v)
202{
203 return (v & 0xff) << 8;
204}
205static inline u32 falcon_falcon_irqdest_target_gptmr_f(u32 v)
206{
207 return (v & 0x1) << 16;
208}
209static inline u32 falcon_falcon_irqdest_target_wdtmr_f(u32 v)
210{
211 return (v & 0x1) << 17;
212}
213static inline u32 falcon_falcon_irqdest_target_mthd_f(u32 v)
214{
215 return (v & 0x1) << 18;
216}
217static inline u32 falcon_falcon_irqdest_target_ctxsw_f(u32 v)
218{
219 return (v & 0x1) << 19;
220}
221static inline u32 falcon_falcon_irqdest_target_halt_f(u32 v)
222{
223 return (v & 0x1) << 20;
224}
225static inline u32 falcon_falcon_irqdest_target_exterr_f(u32 v)
226{
227 return (v & 0x1) << 21;
228}
229static inline u32 falcon_falcon_irqdest_target_swgen0_f(u32 v)
230{
231 return (v & 0x1) << 22;
232}
233static inline u32 falcon_falcon_irqdest_target_swgen1_f(u32 v)
234{
235 return (v & 0x1) << 23;
236}
237static inline u32 falcon_falcon_irqdest_target_ext_f(u32 v)
238{
239 return (v & 0xff) << 24;
240}
241static inline u32 falcon_falcon_curctx_r(void)
242{
243 return 0x00000050;
244}
245static inline u32 falcon_falcon_nxtctx_r(void)
246{
247 return 0x00000054;
248}
249static inline u32 falcon_falcon_mailbox0_r(void)
250{
251 return 0x00000040;
252}
253static inline u32 falcon_falcon_mailbox1_r(void)
254{
255 return 0x00000044;
256}
257static inline u32 falcon_falcon_itfen_r(void)
258{
259 return 0x00000048;
260}
261static inline u32 falcon_falcon_itfen_ctxen_enable_f(void)
262{
263 return 0x1;
264}
265static inline u32 falcon_falcon_idlestate_r(void)
266{
267 return 0x0000004c;
268}
269static inline u32 falcon_falcon_idlestate_falcon_busy_v(u32 r)
270{
271 return (r >> 0) & 0x1;
272}
273static inline u32 falcon_falcon_idlestate_ext_busy_v(u32 r)
274{
275 return (r >> 1) & 0x7fff;
276}
277static inline u32 falcon_falcon_os_r(void)
278{
279 return 0x00000080;
280}
281static inline u32 falcon_falcon_engctl_r(void)
282{
283 return 0x000000a4;
284}
285static inline u32 falcon_falcon_cpuctl_r(void)
286{
287 return 0x00000100;
288}
289static inline u32 falcon_falcon_cpuctl_startcpu_f(u32 v)
290{
291 return (v & 0x1) << 1;
292}
293static inline u32 falcon_falcon_cpuctl_halt_intr_f(u32 v)
294{
295 return (v & 0x1) << 4;
296}
297static inline u32 falcon_falcon_cpuctl_halt_intr_m(void)
298{
299 return 0x1 << 4;
300}
301static inline u32 falcon_falcon_cpuctl_halt_intr_v(u32 r)
302{
303 return (r >> 4) & 0x1;
304}
305static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_f(u32 v)
306{
307 return (v & 0x1) << 6;
308}
309static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_m(void)
310{
311 return 0x1 << 6;
312}
313static inline u32 falcon_falcon_cpuctl_cpuctl_alias_en_v(u32 r)
314{
315 return (r >> 6) & 0x1;
316}
317static inline u32 falcon_falcon_cpuctl_alias_r(void)
318{
319 return 0x00000130;
320}
321static inline u32 falcon_falcon_cpuctl_alias_startcpu_f(u32 v)
322{
323 return (v & 0x1) << 1;
324}
325static inline u32 falcon_falcon_imemc_r(u32 i)
326{
327 return 0x00000180 + i*16;
328}
329static inline u32 falcon_falcon_imemc_offs_f(u32 v)
330{
331 return (v & 0x3f) << 2;
332}
333static inline u32 falcon_falcon_imemc_blk_f(u32 v)
334{
335 return (v & 0xff) << 8;
336}
337static inline u32 falcon_falcon_imemc_aincw_f(u32 v)
338{
339 return (v & 0x1) << 24;
340}
341static inline u32 falcon_falcon_imemd_r(u32 i)
342{
343 return 0x00000184 + i*16;
344}
345static inline u32 falcon_falcon_imemt_r(u32 i)
346{
347 return 0x00000188 + i*16;
348}
349static inline u32 falcon_falcon_sctl_r(void)
350{
351 return 0x00000240;
352}
353static inline u32 falcon_falcon_mmu_phys_sec_r(void)
354{
355 return 0x00100ce4;
356}
357static inline u32 falcon_falcon_bootvec_r(void)
358{
359 return 0x00000104;
360}
361static inline u32 falcon_falcon_bootvec_vec_f(u32 v)
362{
363 return (v & 0xffffffff) << 0;
364}
365static inline u32 falcon_falcon_dmactl_r(void)
366{
367 return 0x0000010c;
368}
369static inline u32 falcon_falcon_dmactl_dmem_scrubbing_m(void)
370{
371 return 0x1 << 1;
372}
373static inline u32 falcon_falcon_dmactl_imem_scrubbing_m(void)
374{
375 return 0x1 << 2;
376}
377static inline u32 falcon_falcon_dmactl_require_ctx_f(u32 v)
378{
379 return (v & 0x1) << 0;
380}
381static inline u32 falcon_falcon_hwcfg_r(void)
382{
383 return 0x00000108;
384}
385static inline u32 falcon_falcon_hwcfg_imem_size_v(u32 r)
386{
387 return (r >> 0) & 0x1ff;
388}
389static inline u32 falcon_falcon_hwcfg_dmem_size_v(u32 r)
390{
391 return (r >> 9) & 0x1ff;
392}
393static inline u32 falcon_falcon_hwcfg1_r(void)
394{
395 return 0x0000012c;
396}
397static inline u32 falcon_falcon_hwcfg1_core_rev_v(u32 r)
398{
399 return (r >> 0) & 0xf;
400}
401static inline u32 falcon_falcon_hwcfg1_security_model_v(u32 r)
402{
403 return (r >> 4) & 0x3;
404}
405static inline u32 falcon_falcon_dmatrfbase_r(void)
406{
407 return 0x00000110;
408}
409static inline u32 falcon_falcon_dmatrfbase1_r(void)
410{
411 return 0x00000128;
412}
413static inline u32 falcon_falcon_dmatrfmoffs_r(void)
414{
415 return 0x00000114;
416}
417static inline u32 falcon_falcon_dmatrfcmd_r(void)
418{
419 return 0x00000118;
420}
421static inline u32 falcon_falcon_dmatrfcmd_imem_f(u32 v)
422{
423 return (v & 0x1) << 4;
424}
425static inline u32 falcon_falcon_dmatrfcmd_write_f(u32 v)
426{
427 return (v & 0x1) << 5;
428}
429static inline u32 falcon_falcon_dmatrfcmd_size_f(u32 v)
430{
431 return (v & 0x7) << 8;
432}
433static inline u32 falcon_falcon_dmatrfcmd_ctxdma_f(u32 v)
434{
435 return (v & 0x7) << 12;
436}
437static inline u32 falcon_falcon_dmatrffboffs_r(void)
438{
439 return 0x0000011c;
440}
441static inline u32 falcon_falcon_exterraddr_r(void)
442{
443 return 0x00000168;
444}
445static inline u32 falcon_falcon_exterrstat_r(void)
446{
447 return 0x0000016c;
448}
449static inline u32 falcon_falcon_exterrstat_valid_m(void)
450{
451 return 0x1 << 31;
452}
453static inline u32 falcon_falcon_exterrstat_valid_v(u32 r)
454{
455 return (r >> 31) & 0x1;
456}
457static inline u32 falcon_falcon_exterrstat_valid_true_v(void)
458{
459 return 0x00000001;
460}
461static inline u32 falcon_falcon_icd_cmd_r(void)
462{
463 return 0x00000200;
464}
465static inline u32 falcon_falcon_icd_cmd_opc_s(void)
466{
467 return 4;
468}
469static inline u32 falcon_falcon_icd_cmd_opc_f(u32 v)
470{
471 return (v & 0xf) << 0;
472}
473static inline u32 falcon_falcon_icd_cmd_opc_m(void)
474{
475 return 0xf << 0;
476}
477static inline u32 falcon_falcon_icd_cmd_opc_v(u32 r)
478{
479 return (r >> 0) & 0xf;
480}
481static inline u32 falcon_falcon_icd_cmd_opc_rreg_f(void)
482{
483 return 0x8;
484}
485static inline u32 falcon_falcon_icd_cmd_opc_rstat_f(void)
486{
487 return 0xe;
488}
489static inline u32 falcon_falcon_icd_cmd_idx_f(u32 v)
490{
491 return (v & 0x1f) << 8;
492}
493static inline u32 falcon_falcon_icd_rdata_r(void)
494{
495 return 0x0000020c;
496}
497static inline u32 falcon_falcon_dmemc_r(u32 i)
498{
499 return 0x000001c0 + i*8;
500}
501static inline u32 falcon_falcon_dmemc_offs_f(u32 v)
502{
503 return (v & 0x3f) << 2;
504}
505static inline u32 falcon_falcon_dmemc_offs_m(void)
506{
507 return 0x3f << 2;
508}
509static inline u32 falcon_falcon_dmemc_blk_f(u32 v)
510{
511 return (v & 0xff) << 8;
512}
513static inline u32 falcon_falcon_dmemc_blk_m(void)
514{
515 return 0xff << 8;
516}
517static inline u32 falcon_falcon_dmemc_aincw_f(u32 v)
518{
519 return (v & 0x1) << 24;
520}
521static inline u32 falcon_falcon_dmemc_aincr_f(u32 v)
522{
523 return (v & 0x1) << 25;
524}
525static inline u32 falcon_falcon_dmemd_r(u32 i)
526{
527 return 0x000001c4 + i*8;
528}
529static inline u32 falcon_falcon_debug1_r(void)
530{
531 return 0x00000090;
532}
533static inline u32 falcon_falcon_debug1_ctxsw_mode_s(void)
534{
535 return 1;
536}
537static inline u32 falcon_falcon_debug1_ctxsw_mode_f(u32 v)
538{
539 return (v & 0x1) << 16;
540}
541static inline u32 falcon_falcon_debug1_ctxsw_mode_m(void)
542{
543 return 0x1 << 16;
544}
545static inline u32 falcon_falcon_debug1_ctxsw_mode_v(u32 r)
546{
547 return (r >> 16) & 0x1;
548}
549static inline u32 falcon_falcon_debug1_ctxsw_mode_init_f(void)
550{
551 return 0x0;
552}
553static inline u32 falcon_falcon_debuginfo_r(void)
554{
555 return 0x00000094;
556}
557#endif