diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/pstate/pstate.c | 35 |
4 files changed, 32 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f71ddc2c..8f35e2c9 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1034,6 +1034,9 @@ struct gpu_ops { | |||
1034 | void (*mclk_deinit)(struct gk20a *g); | 1034 | void (*mclk_deinit)(struct gk20a *g); |
1035 | int (*mclk_change)(struct gk20a *g, u16 val); | 1035 | int (*mclk_change)(struct gk20a *g, u16 val); |
1036 | bool split_rail_support; | 1036 | bool split_rail_support; |
1037 | bool support_clk_freq_controller; | ||
1038 | bool support_pmgr_domain; | ||
1039 | bool support_lpwr_pg; | ||
1037 | } clk; | 1040 | } clk; |
1038 | struct { | 1041 | struct { |
1039 | u32 (*get_arbiter_clk_domains)(struct gk20a *g); | 1042 | u32 (*get_arbiter_clk_domains)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index c87414d0..7cfe4d76 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -833,6 +833,9 @@ int gp106_init_hal(struct gk20a *g) | |||
833 | g->pmu_lsf_pmu_wpr_init_done = 0; | 833 | g->pmu_lsf_pmu_wpr_init_done = 0; |
834 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 834 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
835 | gops->clk.split_rail_support = true; | 835 | gops->clk.split_rail_support = true; |
836 | gops->clk.support_clk_freq_controller = true; | ||
837 | gops->clk.support_pmgr_domain = true; | ||
838 | gops->clk.support_lpwr_pg = true; | ||
836 | 839 | ||
837 | g->name = "gp10x"; | 840 | g->name = "gp10x"; |
838 | 841 | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index f0926402..30d19027 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -908,6 +908,9 @@ int gv100_init_hal(struct gk20a *g) | |||
908 | g->pmu_lsf_pmu_wpr_init_done = 0; | 908 | g->pmu_lsf_pmu_wpr_init_done = 0; |
909 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 909 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
910 | gops->clk.split_rail_support = false; | 910 | gops->clk.split_rail_support = false; |
911 | gops->clk.support_clk_freq_controller = false; | ||
912 | gops->clk.support_pmgr_domain = false; | ||
913 | gops->clk.support_lpwr_pg = false; | ||
911 | 914 | ||
912 | g->name = "gv10x"; | 915 | g->name = "gv10x"; |
913 | 916 | ||
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c index 3d6a436d..6c9d7736 100644 --- a/drivers/gpu/nvgpu/pstate/pstate.c +++ b/drivers/gpu/nvgpu/pstate/pstate.c | |||
@@ -96,15 +96,23 @@ int gk20a_init_pstate_support(struct gk20a *g) | |||
96 | if (err) | 96 | if (err) |
97 | return err; | 97 | return err; |
98 | 98 | ||
99 | err = pmgr_domain_sw_setup(g); | 99 | if(g->ops.clk.support_pmgr_domain) { |
100 | if (err) | 100 | err = pmgr_domain_sw_setup(g); |
101 | return err; | 101 | if (err) |
102 | return err; | ||
103 | } | ||
102 | 104 | ||
103 | err = clk_freq_controller_sw_setup(g); | 105 | if (g->ops.clk.support_clk_freq_controller) { |
104 | if (err) | 106 | err = clk_freq_controller_sw_setup(g); |
105 | return err; | 107 | if (err) |
108 | return err; | ||
109 | } | ||
106 | 110 | ||
107 | err = nvgpu_lpwr_pg_setup(g); | 111 | if(g->ops.clk.support_lpwr_pg) { |
112 | err = nvgpu_lpwr_pg_setup(g); | ||
113 | if (err) | ||
114 | return err; | ||
115 | } | ||
108 | 116 | ||
109 | return err; | 117 | return err; |
110 | } | 118 | } |
@@ -176,10 +184,11 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
176 | if (err) | 184 | if (err) |
177 | return err; | 185 | return err; |
178 | 186 | ||
179 | err = clk_freq_controller_pmu_setup(g); | 187 | if (g->ops.clk.support_clk_freq_controller) { |
180 | if (err) | 188 | err = clk_freq_controller_pmu_setup(g); |
181 | return err; | 189 | if (err) |
182 | 190 | return err; | |
191 | } | ||
183 | err = clk_pmu_vin_load(g); | 192 | err = clk_pmu_vin_load(g); |
184 | if (err) | 193 | if (err) |
185 | return err; | 194 | return err; |
@@ -188,7 +197,9 @@ int gk20a_init_pstate_pmu_support(struct gk20a *g) | |||
188 | if (err) | 197 | if (err) |
189 | return err; | 198 | return err; |
190 | 199 | ||
191 | err = pmgr_domain_pmu_setup(g); | 200 | if (g->ops.clk.support_pmgr_domain) |
201 | err = pmgr_domain_pmu_setup(g); | ||
202 | |||
192 | return err; | 203 | return err; |
193 | } | 204 | } |
194 | 205 | ||