diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 23 |
1 files changed, 13 insertions, 10 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index f7404f81..79a3ddc5 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -31,8 +31,6 @@ | |||
31 | #include "hw_fuse_gm20b.h" | 31 | #include "hw_fuse_gm20b.h" |
32 | #include "clk_gm20b.h" | 32 | #include "clk_gm20b.h" |
33 | 33 | ||
34 | #define ALLOW_NON_CALIBRATED_NA_MODE 1 | ||
35 | |||
36 | #define gk20a_dbg_clk(fmt, arg...) \ | 34 | #define gk20a_dbg_clk(fmt, arg...) \ |
37 | gk20a_dbg(gpu_dbg_clk, fmt, ##arg) | 35 | gk20a_dbg(gpu_dbg_clk, fmt, ##arg) |
38 | 36 | ||
@@ -1069,7 +1067,6 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1069 | struct clk_gk20a *clk = &g->clk; | 1067 | struct clk_gk20a *clk = &g->clk; |
1070 | unsigned long safe_rate; | 1068 | unsigned long safe_rate; |
1071 | struct clk *ref; | 1069 | struct clk *ref; |
1072 | bool calibrated; | ||
1073 | 1070 | ||
1074 | gk20a_dbg_fn(""); | 1071 | gk20a_dbg_fn(""); |
1075 | 1072 | ||
@@ -1120,14 +1117,20 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1120 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; | 1117 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; |
1121 | clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL); | 1118 | clk->gpc_pll.freq /= pl_to_div(clk->gpc_pll.PL); |
1122 | 1119 | ||
1123 | calibrated = !clk_config_calibration_params(g); | 1120 | /* |
1121 | * All production parts should have ADC fuses burnt. Therefore, check | ||
1122 | * ADC fuses always, regardless of whether NA mode is selected; and if | ||
1123 | * NA mode is indeed selected, and part can support it, switch to NA | ||
1124 | * mode even when ADC calibration is not fused; less accurate s/w | ||
1125 | * self-calibration will be used for those parts. | ||
1126 | */ | ||
1127 | clk_config_calibration_params(g); | ||
1124 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL | 1128 | #ifdef CONFIG_TEGRA_USE_NA_GPCPLL |
1125 | if (ALLOW_NON_CALIBRATED_NA_MODE || calibrated) { | 1129 | if (tegra_fuse_can_use_na_gpcpll()) { |
1126 | /* NA mode is supported only at max update rate 38.4 MHz */ | 1130 | /* NA mode is supported only at max update rate 38.4 MHz */ |
1127 | if (clk->gpc_pll.clk_in == gpc_pll_params.max_u) { | 1131 | BUG_ON(clk->gpc_pll.clk_in != gpc_pll_params.max_u); |
1128 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; | 1132 | clk->gpc_pll.mode = GPC_PLL_MODE_DVFS; |
1129 | gpc_pll_params.min_u = gpc_pll_params.max_u; | 1133 | gpc_pll_params.min_u = gpc_pll_params.max_u; |
1130 | } | ||
1131 | } | 1134 | } |
1132 | #endif | 1135 | #endif |
1133 | 1136 | ||
@@ -1136,7 +1139,7 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1136 | clk->sw_ready = true; | 1139 | clk->sw_ready = true; |
1137 | 1140 | ||
1138 | gk20a_dbg_fn("done"); | 1141 | gk20a_dbg_fn("done"); |
1139 | pr_info("GM20b GPCPLL initial settings:%s M=%u, N=%u, P=%u\n", | 1142 | pr_info("gm20b gpu.0 GPCPLL initial settings:%s M=%u, N=%u, P=%u\n", |
1140 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", | 1143 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", |
1141 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); | 1144 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); |
1142 | return 0; | 1145 | return 0; |