diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ce2_gm20b.c | 28 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ce2_gm20b.h | 29 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ce_gp10b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 6 |
10 files changed, 19 insertions, 76 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu index c754fbd4..ffe78097 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu +++ b/drivers/gpu/nvgpu/Makefile.nvgpu | |||
@@ -99,7 +99,6 @@ nvgpu-y := \ | |||
99 | gm20b/hal_gm20b.o \ | 99 | gm20b/hal_gm20b.o \ |
100 | gm20b/bus_gm20b.o \ | 100 | gm20b/bus_gm20b.o \ |
101 | gm20b/ltc_gm20b.o \ | 101 | gm20b/ltc_gm20b.o \ |
102 | gm20b/ce2_gm20b.o \ | ||
103 | gm20b/gr_gm20b.o \ | 102 | gm20b/gr_gm20b.o \ |
104 | gm20b/clk_gm20b.o \ | 103 | gm20b/clk_gm20b.o \ |
105 | gm20b/fb_gm20b.o \ | 104 | gm20b/fb_gm20b.o \ |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c index b0f65647..f50fec13 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c | |||
@@ -82,11 +82,6 @@ int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
82 | } | 82 | } |
83 | return ops; | 83 | return ops; |
84 | } | 84 | } |
85 | void gk20a_init_ce2(struct gpu_ops *gops) | ||
86 | { | ||
87 | gops->ce2.isr_stall = gk20a_ce2_isr; | ||
88 | gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr; | ||
89 | } | ||
90 | 85 | ||
91 | /* static CE app api */ | 86 | /* static CE app api */ |
92 | static void gk20a_ce_notify_all_user(struct gk20a *g, u32 event) | 87 | static void gk20a_ce_notify_all_user(struct gk20a *g, u32 event) |
diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h index 93905ab9..03117043 100644 --- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.h | |||
@@ -24,7 +24,6 @@ | |||
24 | #include "channel_gk20a.h" | 24 | #include "channel_gk20a.h" |
25 | #include "tsg_gk20a.h" | 25 | #include "tsg_gk20a.h" |
26 | 26 | ||
27 | void gk20a_init_ce2(struct gpu_ops *gops); | ||
28 | void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 27 | void gk20a_ce2_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
29 | int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 28 | int gk20a_ce2_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
30 | 29 | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ce2_gm20b.c b/drivers/gpu/nvgpu/gm20b/ce2_gm20b.c deleted file mode 100644 index a90a9b5b..00000000 --- a/drivers/gpu/nvgpu/gm20b/ce2_gm20b.c +++ /dev/null | |||
@@ -1,28 +0,0 @@ | |||
1 | /* | ||
2 | * GK20A Graphics Copy Engine (gr host) | ||
3 | * | ||
4 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * This program is free software; you can redistribute it and/or modify it | ||
7 | * under the terms and conditions of the GNU General Public License, | ||
8 | * version 2, as published by the Free Software Foundation. | ||
9 | * | ||
10 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
13 | * more details. | ||
14 | * | ||
15 | * You should have received a copy of the GNU General Public License along with | ||
16 | * this program; if not, write to the Free Software Foundation, Inc., | ||
17 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
18 | */ | ||
19 | |||
20 | /*TODO: remove uncecessary */ | ||
21 | #include "gk20a/gk20a.h" | ||
22 | #include "ce2_gm20b.h" | ||
23 | |||
24 | void gm20b_init_ce2(struct gpu_ops *gops) | ||
25 | { | ||
26 | gops->ce2.isr_stall = gk20a_ce2_isr; | ||
27 | gops->ce2.isr_nonstall = gk20a_ce2_nonstall_isr; | ||
28 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/ce2_gm20b.h b/drivers/gpu/nvgpu/gm20b/ce2_gm20b.h deleted file mode 100644 index 10d7ef8c..00000000 --- a/drivers/gpu/nvgpu/gm20b/ce2_gm20b.h +++ /dev/null | |||
@@ -1,29 +0,0 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gk20a/fifo_gk20a.h | ||
3 | * | ||
4 | * GK20A graphics copy engine (gr host) | ||
5 | * | ||
6 | * Copyright (c) 2011-2015, NVIDIA CORPORATION. All rights reserved. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms and conditions of the GNU General Public License, | ||
10 | * version 2, as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License along with | ||
18 | * this program; if not, write to the Free Software Foundation, Inc., | ||
19 | * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. | ||
20 | */ | ||
21 | #ifndef __CE2_GM20B_H__ | ||
22 | #define __CE2_GM20B_H__ | ||
23 | |||
24 | #include "gk20a/channel_gk20a.h" | ||
25 | #include "gk20a/tsg_gk20a.h" | ||
26 | |||
27 | void gm20b_init_ce2(struct gpu_ops *gops); | ||
28 | |||
29 | #endif /*__CE2_GM20B_H__*/ | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 228e1a97..c89f3746 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -14,6 +14,7 @@ | |||
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/ce2_gk20a.h" | ||
17 | #include "gk20a/dbg_gpu_gk20a.h" | 18 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/fifo_gk20a.h" | 19 | #include "gk20a/fifo_gk20a.h" |
19 | #include "gk20a/css_gr_gk20a.h" | 20 | #include "gk20a/css_gr_gk20a.h" |
@@ -24,7 +25,6 @@ | |||
24 | #include "gk20a/regops_gk20a.h" | 25 | #include "gk20a/regops_gk20a.h" |
25 | 26 | ||
26 | #include "ltc_gm20b.h" | 27 | #include "ltc_gm20b.h" |
27 | #include "ce2_gm20b.h" | ||
28 | #include "gr_gm20b.h" | 28 | #include "gr_gm20b.h" |
29 | #include "ltc_gm20b.h" | 29 | #include "ltc_gm20b.h" |
30 | #include "fb_gm20b.h" | 30 | #include "fb_gm20b.h" |
@@ -158,6 +158,10 @@ static const struct gpu_ops gm20b_ops = { | |||
158 | .sync_debugfs = gm20b_ltc_sync_debugfs, | 158 | .sync_debugfs = gm20b_ltc_sync_debugfs, |
159 | #endif | 159 | #endif |
160 | }, | 160 | }, |
161 | .ce2 = { | ||
162 | .isr_stall = gk20a_ce2_isr, | ||
163 | .isr_nonstall = gk20a_ce2_nonstall_isr, | ||
164 | }, | ||
161 | .clock_gating = { | 165 | .clock_gating = { |
162 | .slcg_bus_load_gating_prod = | 166 | .slcg_bus_load_gating_prod = |
163 | gm20b_slcg_bus_load_gating_prod, | 167 | gm20b_slcg_bus_load_gating_prod, |
@@ -332,6 +336,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
332 | u32 val; | 336 | u32 val; |
333 | 337 | ||
334 | gops->ltc = gm20b_ops.ltc; | 338 | gops->ltc = gm20b_ops.ltc; |
339 | gops->ce2 = gm20b_ops.ce2; | ||
335 | gops->clock_gating = gm20b_ops.clock_gating; | 340 | gops->clock_gating = gm20b_ops.clock_gating; |
336 | gops->fifo = gm20b_ops.fifo; | 341 | gops->fifo = gm20b_ops.fifo; |
337 | gops->mc = gm20b_ops.mc; | 342 | gops->mc = gm20b_ops.mc; |
@@ -384,7 +389,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 389 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
385 | gm20b_init_gr(g); | 390 | gm20b_init_gr(g); |
386 | gm20b_init_fb(gops); | 391 | gm20b_init_fb(gops); |
387 | gm20b_init_ce2(gops); | ||
388 | gm20b_init_gr_ctx(gops); | 392 | gm20b_init_gr_ctx(gops); |
389 | gm20b_init_mm(gops); | 393 | gm20b_init_mm(gops); |
390 | gm20b_init_pmu_ops(g); | 394 | gm20b_init_pmu_ops(g); |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 49c4b358..227b22e6 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -203,6 +203,10 @@ static const struct gpu_ops gp106_ops = { | |||
203 | .sync_debugfs = gp10b_ltc_sync_debugfs, | 203 | .sync_debugfs = gp10b_ltc_sync_debugfs, |
204 | #endif | 204 | #endif |
205 | }, | 205 | }, |
206 | .ce2 = { | ||
207 | .isr_stall = gp10b_ce_isr, | ||
208 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
209 | }, | ||
206 | .clock_gating = { | 210 | .clock_gating = { |
207 | .slcg_bus_load_gating_prod = | 211 | .slcg_bus_load_gating_prod = |
208 | gp106_slcg_bus_load_gating_prod, | 212 | gp106_slcg_bus_load_gating_prod, |
@@ -396,6 +400,7 @@ int gp106_init_hal(struct gk20a *g) | |||
396 | gk20a_dbg_fn(""); | 400 | gk20a_dbg_fn(""); |
397 | 401 | ||
398 | gops->ltc = gp106_ops.ltc; | 402 | gops->ltc = gp106_ops.ltc; |
403 | gops->ce2 = gp106_ops.ce2; | ||
399 | gops->clock_gating = gp106_ops.clock_gating; | 404 | gops->clock_gating = gp106_ops.clock_gating; |
400 | gops->fifo = gp106_ops.fifo; | 405 | gops->fifo = gp106_ops.fifo; |
401 | gops->mc = gp106_ops.mc; | 406 | gops->mc = gp106_ops.mc; |
@@ -424,7 +429,6 @@ int gp106_init_hal(struct gk20a *g) | |||
424 | gp106_init_gr(g); | 429 | gp106_init_gr(g); |
425 | gp10b_init_fecs_trace_ops(gops); | 430 | gp10b_init_fecs_trace_ops(gops); |
426 | gp106_init_fb(gops); | 431 | gp106_init_fb(gops); |
427 | gp10b_init_ce(gops); | ||
428 | gp106_init_gr_ctx(gops); | 432 | gp106_init_gr_ctx(gops); |
429 | gp106_init_mm(gops); | 433 | gp106_init_mm(gops); |
430 | gp106_init_pmu_ops(g); | 434 | gp106_init_pmu_ops(g); |
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c index 1fff37fb..59a6ee21 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.c | |||
@@ -54,7 +54,7 @@ void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
54 | return; | 54 | return; |
55 | } | 55 | } |
56 | 56 | ||
57 | static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | 57 | int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) |
58 | { | 58 | { |
59 | int ops = 0; | 59 | int ops = 0; |
60 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); | 60 | u32 ce_intr = gk20a_readl(g, ce_intr_status_r(inst_id)); |
@@ -70,8 +70,3 @@ static int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base) | |||
70 | 70 | ||
71 | return ops; | 71 | return ops; |
72 | } | 72 | } |
73 | void gp10b_init_ce(struct gpu_ops *gops) | ||
74 | { | ||
75 | gops->ce2.isr_stall = gp10b_ce_isr; | ||
76 | gops->ce2.isr_nonstall = gp10b_ce_nonstall_isr; | ||
77 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h index 134c2ddb..f88e0ae1 100644 --- a/drivers/gpu/nvgpu/gp10b/ce_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/ce_gp10b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pascal GPU series Copy Engine. | 2 | * Pascal GPU series Copy Engine. |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -21,7 +21,7 @@ | |||
21 | #include "gk20a/channel_gk20a.h" | 21 | #include "gk20a/channel_gk20a.h" |
22 | #include "gk20a/tsg_gk20a.h" | 22 | #include "gk20a/tsg_gk20a.h" |
23 | 23 | ||
24 | void gp10b_init_ce(struct gpu_ops *gops); | ||
25 | void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | 24 | void gp10b_ce_isr(struct gk20a *g, u32 inst_id, u32 pri_base); |
25 | int gp10b_ce_nonstall_isr(struct gk20a *g, u32 inst_id, u32 pri_base); | ||
26 | 26 | ||
27 | #endif /*__CE2_GP10B_H__*/ | 27 | #endif /*__CE2_GP10B_H__*/ |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 6b4fbf40..feac284b 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -165,6 +165,10 @@ static const struct gpu_ops gp10b_ops = { | |||
165 | .sync_debugfs = gp10b_ltc_sync_debugfs, | 165 | .sync_debugfs = gp10b_ltc_sync_debugfs, |
166 | #endif | 166 | #endif |
167 | }, | 167 | }, |
168 | .ce2 = { | ||
169 | .isr_stall = gp10b_ce_isr, | ||
170 | .isr_nonstall = gp10b_ce_nonstall_isr, | ||
171 | }, | ||
168 | .clock_gating = { | 172 | .clock_gating = { |
169 | .slcg_bus_load_gating_prod = | 173 | .slcg_bus_load_gating_prod = |
170 | gp10b_slcg_bus_load_gating_prod, | 174 | gp10b_slcg_bus_load_gating_prod, |
@@ -345,6 +349,7 @@ int gp10b_init_hal(struct gk20a *g) | |||
345 | u32 val; | 349 | u32 val; |
346 | 350 | ||
347 | gops->ltc = gp10b_ops.ltc; | 351 | gops->ltc = gp10b_ops.ltc; |
352 | gops->ce2 = gp10b_ops.ce2; | ||
348 | gops->clock_gating = gp10b_ops.clock_gating; | 353 | gops->clock_gating = gp10b_ops.clock_gating; |
349 | gops->fifo = gp10b_ops.fifo; | 354 | gops->fifo = gp10b_ops.fifo; |
350 | gops->mc = gp10b_ops.mc; | 355 | gops->mc = gp10b_ops.mc; |
@@ -407,7 +412,6 @@ int gp10b_init_hal(struct gk20a *g) | |||
407 | gp10b_init_gr(g); | 412 | gp10b_init_gr(g); |
408 | gp10b_init_fecs_trace_ops(gops); | 413 | gp10b_init_fecs_trace_ops(gops); |
409 | gp10b_init_fb(gops); | 414 | gp10b_init_fb(gops); |
410 | gp10b_init_ce(gops); | ||
411 | gp10b_init_gr_ctx(gops); | 415 | gp10b_init_gr_ctx(gops); |
412 | gp10b_init_mm(gops); | 416 | gp10b_init_mm(gops); |
413 | gp10b_init_pmu_ops(g); | 417 | gp10b_init_pmu_ops(g); |