diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fuse_gm20b.c | 90 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fuse_gm20b.h | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fuse_gp106.c | 35 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/fuse_gp106.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | 91 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | 32 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 27 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 21 |
18 files changed, 515 insertions, 76 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 72946fc0..a4ef22e5 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -114,6 +114,7 @@ nvgpu-y := \ | |||
114 | gm20b/mm_gm20b.o \ | 114 | gm20b/mm_gm20b.o \ |
115 | gm20b/regops_gm20b.o \ | 115 | gm20b/regops_gm20b.o \ |
116 | gm20b/therm_gm20b.o \ | 116 | gm20b/therm_gm20b.o \ |
117 | gm20b/fuse_gm20b.o \ | ||
117 | boardobj/boardobj.o \ | 118 | boardobj/boardobj.o \ |
118 | boardobj/boardobjgrp.o \ | 119 | boardobj/boardobjgrp.o \ |
119 | boardobj/boardobjgrpmask.o \ | 120 | boardobj/boardobjgrpmask.o \ |
@@ -166,6 +167,7 @@ nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | |||
166 | common/linux/vgpu/css_vgpu.o \ | 167 | common/linux/vgpu/css_vgpu.o \ |
167 | common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \ | 168 | common/linux/vgpu/gm20b/vgpu_hal_gm20b.o \ |
168 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ | 169 | common/linux/vgpu/gm20b/vgpu_gr_gm20b.o \ |
170 | common/linux/vgpu/gm20b/vgpu_fuse_gm20b.o \ | ||
169 | common/linux/vgpu/sysfs_vgpu.o | 171 | common/linux/vgpu/sysfs_vgpu.o |
170 | 172 | ||
171 | nvgpu-$(CONFIG_COMMON_CLK) += \ | 173 | nvgpu-$(CONFIG_COMMON_CLK) += \ |
@@ -195,6 +197,7 @@ nvgpu-y += \ | |||
195 | gp10b/fecs_trace_gp10b.o \ | 197 | gp10b/fecs_trace_gp10b.o \ |
196 | gp10b/priv_ring_gp10b.o \ | 198 | gp10b/priv_ring_gp10b.o \ |
197 | gp10b/gp10b.o \ | 199 | gp10b/gp10b.o \ |
200 | gp10b/fuse_gp10b.o \ | ||
198 | gp106/hal_gp106.o \ | 201 | gp106/hal_gp106.o \ |
199 | gp106/mm_gp106.o \ | 202 | gp106/mm_gp106.o \ |
200 | gp106/flcn_gp106.o \ | 203 | gp106/flcn_gp106.o \ |
@@ -208,6 +211,7 @@ nvgpu-y += \ | |||
208 | gp106/fb_gp106.o \ | 211 | gp106/fb_gp106.o \ |
209 | gp106/regops_gp106.o \ | 212 | gp106/regops_gp106.o \ |
210 | gp106/bios_gp106.o \ | 213 | gp106/bios_gp106.o \ |
214 | gp106/fuse_gp106.o \ | ||
211 | pstate/pstate.o \ | 215 | pstate/pstate.o \ |
212 | clk/clk_vin.o \ | 216 | clk/clk_vin.o \ |
213 | clk/clk_fll.o \ | 217 | clk/clk_fll.o \ |
@@ -247,6 +251,7 @@ nvgpu-$(CONFIG_TEGRA_GK20A) += common/linux/platform_gp10b_tegra.o | |||
247 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ | 251 | nvgpu-$(CONFIG_TEGRA_GR_VIRTUALIZATION) += \ |
248 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ | 252 | common/linux/vgpu/gp10b/vgpu_hal_gp10b.o \ |
249 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ | 253 | common/linux/vgpu/gp10b/vgpu_gr_gp10b.o \ |
254 | common/linux/vgpu/gp10b/vgpu_fuse_gp10b.o \ | ||
250 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o | 255 | common/linux/vgpu/gp10b/vgpu_mm_gp10b.o |
251 | 256 | ||
252 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) | 257 | ifeq ($(CONFIG_ARCH_TEGRA_19x_SOC),y) |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c new file mode 100644 index 00000000..2ab745ab --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.c | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/enabled.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g) | ||
28 | { | ||
29 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
30 | |||
31 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
32 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
33 | else | ||
34 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
35 | |||
36 | return 0; | ||
37 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h new file mode 100644 index 00000000..39da09fa --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_fuse_gm20b.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _VGPU_GM20B_FUSE | ||
24 | #define _VGPU_GM20B_FUSE | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | int vgpu_gm20b_fuse_check_priv_security(struct gk20a *g); | ||
29 | |||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c index b9d3f734..0e560981 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gm20b/vgpu_hal_gm20b.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "common/linux/vgpu/fecs_trace_vgpu.h" | 24 | #include "common/linux/vgpu/fecs_trace_vgpu.h" |
25 | #include "common/linux/vgpu/css_vgpu.h" | 25 | #include "common/linux/vgpu/css_vgpu.h" |
26 | #include "vgpu_gr_gm20b.h" | 26 | #include "vgpu_gr_gm20b.h" |
27 | #include "vgpu_fuse_gm20b.h" | ||
27 | 28 | ||
28 | #include "gk20a/bus_gk20a.h" | 29 | #include "gk20a/bus_gk20a.h" |
29 | #include "gk20a/flcn_gk20a.h" | 30 | #include "gk20a/flcn_gk20a.h" |
@@ -456,6 +457,9 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
456 | .priv_ring = { | 457 | .priv_ring = { |
457 | .isr = gk20a_priv_ring_isr, | 458 | .isr = gk20a_priv_ring_isr, |
458 | }, | 459 | }, |
460 | .fuse = { | ||
461 | .check_priv_security = vgpu_gm20b_fuse_check_priv_security, | ||
462 | }, | ||
459 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | 463 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, |
460 | .get_litter_value = gm20b_get_litter_value, | 464 | .get_litter_value = gm20b_get_litter_value, |
461 | }; | 465 | }; |
@@ -463,7 +467,6 @@ static const struct gpu_ops vgpu_gm20b_ops = { | |||
463 | int vgpu_gm20b_init_hal(struct gk20a *g) | 467 | int vgpu_gm20b_init_hal(struct gk20a *g) |
464 | { | 468 | { |
465 | struct gpu_ops *gops = &g->ops; | 469 | struct gpu_ops *gops = &g->ops; |
466 | u32 val; | ||
467 | 470 | ||
468 | gops->ltc = vgpu_gm20b_ops.ltc; | 471 | gops->ltc = vgpu_gm20b_ops.ltc; |
469 | gops->ce2 = vgpu_gm20b_ops.ce2; | 472 | gops->ce2 = vgpu_gm20b_ops.ce2; |
@@ -499,26 +502,19 @@ int vgpu_gm20b_init_hal(struct gk20a *g) | |||
499 | 502 | ||
500 | gops->priv_ring = vgpu_gm20b_ops.priv_ring; | 503 | gops->priv_ring = vgpu_gm20b_ops.priv_ring; |
501 | 504 | ||
505 | gops->fuse = vgpu_gm20b_ops.fuse; | ||
506 | |||
502 | /* Lone functions */ | 507 | /* Lone functions */ |
503 | gops->chip_init_gpu_characteristics = | 508 | gops->chip_init_gpu_characteristics = |
504 | vgpu_gm20b_ops.chip_init_gpu_characteristics; | 509 | vgpu_gm20b_ops.chip_init_gpu_characteristics; |
505 | gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; | 510 | gops->get_litter_value = vgpu_gm20b_ops.get_litter_value; |
506 | 511 | ||
507 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 512 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
508 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
509 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 513 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
510 | 514 | ||
511 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 515 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
512 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 516 | if (gops->fuse.check_priv_security(g)) |
513 | } else { | 517 | return -EINVAL; /* Do not boot gpu */ |
514 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
515 | if (!val) { | ||
516 | gk20a_dbg_info("priv security is disabled in HW"); | ||
517 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
518 | } else { | ||
519 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
520 | } | ||
521 | } | ||
522 | 518 | ||
523 | /* priv security dependent ops */ | 519 | /* priv security dependent ops */ |
524 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 520 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c new file mode 100644 index 00000000..5ee5d1f6 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.c | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #include <nvgpu/enabled.h> | ||
24 | |||
25 | #include "gk20a/gk20a.h" | ||
26 | |||
27 | int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g) | ||
28 | { | ||
29 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
30 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
31 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
32 | } else { | ||
33 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
34 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
35 | } | ||
36 | |||
37 | return 0; | ||
38 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h new file mode 100644 index 00000000..2ec8f284 --- /dev/null +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_fuse_gp10b.h | |||
@@ -0,0 +1,30 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
5 | * copy of this software and associated documentation files (the "Software"), | ||
6 | * to deal in the Software without restriction, including without limitation | ||
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
8 | * and/or sell copies of the Software, and to permit persons to whom the | ||
9 | * Software is furnished to do so, subject to the following conditions: | ||
10 | * | ||
11 | * The above copyright notice and this permission notice shall be included in | ||
12 | * all copies or substantial portions of the Software. | ||
13 | * | ||
14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
17 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
18 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
19 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
20 | * DEALINGS IN THE SOFTWARE. | ||
21 | */ | ||
22 | |||
23 | #ifndef _VGPU_GP10B_FUSE | ||
24 | #define _VGPU_GP10B_FUSE | ||
25 | |||
26 | struct gk20a; | ||
27 | |||
28 | int vgpu_gp10b_fuse_check_priv_security(struct gk20a *g); | ||
29 | |||
30 | #endif | ||
diff --git a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c index 78f88d4d..b35cac90 100644 --- a/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/common/linux/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -27,6 +27,7 @@ | |||
27 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" | 27 | #include "common/linux/vgpu/gm20b/vgpu_gr_gm20b.h" |
28 | #include "vgpu_gr_gp10b.h" | 28 | #include "vgpu_gr_gp10b.h" |
29 | #include "vgpu_mm_gp10b.h" | 29 | #include "vgpu_mm_gp10b.h" |
30 | #include "vgpu_fuse_gp10b.h" | ||
30 | 31 | ||
31 | #include "gk20a/bus_gk20a.h" | 32 | #include "gk20a/bus_gk20a.h" |
32 | #include "gk20a/pramin_gk20a.h" | 33 | #include "gk20a/pramin_gk20a.h" |
@@ -498,6 +499,9 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
498 | .priv_ring = { | 499 | .priv_ring = { |
499 | .isr = gp10b_priv_ring_isr, | 500 | .isr = gp10b_priv_ring_isr, |
500 | }, | 501 | }, |
502 | .fuse = { | ||
503 | .check_priv_security = vgpu_gp10b_fuse_check_priv_security, | ||
504 | }, | ||
501 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, | 505 | .chip_init_gpu_characteristics = vgpu_init_gpu_characteristics, |
502 | .get_litter_value = gp10b_get_litter_value, | 506 | .get_litter_value = gp10b_get_litter_value, |
503 | }; | 507 | }; |
@@ -505,7 +509,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
505 | int vgpu_gp10b_init_hal(struct gk20a *g) | 509 | int vgpu_gp10b_init_hal(struct gk20a *g) |
506 | { | 510 | { |
507 | struct gpu_ops *gops = &g->ops; | 511 | struct gpu_ops *gops = &g->ops; |
508 | u32 val; | ||
509 | 512 | ||
510 | gops->ltc = vgpu_gp10b_ops.ltc; | 513 | gops->ltc = vgpu_gp10b_ops.ltc; |
511 | gops->ce2 = vgpu_gp10b_ops.ce2; | 514 | gops->ce2 = vgpu_gp10b_ops.ce2; |
@@ -531,6 +534,8 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
531 | 534 | ||
532 | gops->priv_ring = vgpu_gp10b_ops.priv_ring; | 535 | gops->priv_ring = vgpu_gp10b_ops.priv_ring; |
533 | 536 | ||
537 | gops->fuse = vgpu_gp10b_ops.fuse; | ||
538 | |||
534 | /* Lone Functions */ | 539 | /* Lone Functions */ |
535 | gops->chip_init_gpu_characteristics = | 540 | gops->chip_init_gpu_characteristics = |
536 | vgpu_gp10b_ops.chip_init_gpu_characteristics; | 541 | vgpu_gp10b_ops.chip_init_gpu_characteristics; |
@@ -539,23 +544,9 @@ int vgpu_gp10b_init_hal(struct gk20a *g) | |||
539 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 544 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
540 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 545 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
541 | 546 | ||
542 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 547 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
543 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 548 | if (gops->fuse.check_priv_security(g)) |
544 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 549 | return -EINVAL; /* Do not boot gpu */ |
545 | } else if (g->is_virtual) { | ||
546 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
547 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
548 | } else { | ||
549 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
550 | if (val) { | ||
551 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
552 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
553 | } else { | ||
554 | gk20a_dbg_info("priv security is disabled in HW"); | ||
555 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
556 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
557 | } | ||
558 | } | ||
559 | 550 | ||
560 | /* priv security dependent ops */ | 551 | /* priv security dependent ops */ |
561 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 552 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 8d8bfbec..8d6db4c7 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1024,6 +1024,10 @@ struct gpu_ops { | |||
1024 | struct { | 1024 | struct { |
1025 | void (*isr)(struct gk20a *g); | 1025 | void (*isr)(struct gk20a *g); |
1026 | } priv_ring; | 1026 | } priv_ring; |
1027 | struct { | ||
1028 | int (*check_priv_security)(struct gk20a *g); | ||
1029 | } fuse; | ||
1030 | |||
1027 | }; | 1031 | }; |
1028 | 1032 | ||
1029 | struct nvgpu_bios_ucode { | 1033 | struct nvgpu_bios_ucode { |
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c new file mode 100644 index 00000000..165d5b43 --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.c | |||
@@ -0,0 +1,90 @@ | |||
1 | /* | ||
2 | * GM20B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "fuse_gm20b.h" | ||
32 | |||
33 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | ||
34 | |||
35 | int gm20b_fuse_check_priv_security(struct gk20a *g) | ||
36 | { | ||
37 | u32 gcplex_config; | ||
38 | |||
39 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
40 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
41 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
42 | nvgpu_log(g, gpu_dbg_info, "priv sec is enabled in fmodel"); | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
47 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
48 | return -EINVAL; | ||
49 | } | ||
50 | |||
51 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
52 | |||
53 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
54 | /* | ||
55 | * all falcons have to boot in LS mode and this needs | ||
56 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
57 | * set to 0. In this case gmmu tries to pull wpr | ||
58 | * and vpr settings from tegra mc | ||
59 | */ | ||
60 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
61 | if ((gcplex_config & | ||
62 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
63 | !(gcplex_config & | ||
64 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
65 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
66 | nvgpu_log(g, gpu_dbg_info, | ||
67 | "gcplex_config = 0x%08x, " | ||
68 | "secure mode: ACR debug", | ||
69 | gcplex_config); | ||
70 | else | ||
71 | nvgpu_log(g, gpu_dbg_info, | ||
72 | "gcplex_config = 0x%08x, " | ||
73 | "secure mode: ACR non debug", | ||
74 | gcplex_config); | ||
75 | } else { | ||
76 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
77 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
78 | "with priv_sec_en", gcplex_config); | ||
79 | /* do not try to boot GPU */ | ||
80 | return -EINVAL; | ||
81 | } | ||
82 | } else { | ||
83 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
84 | nvgpu_log(g, gpu_dbg_info, | ||
85 | "gcplex_config = 0x%08x, non secure mode", | ||
86 | gcplex_config); | ||
87 | } | ||
88 | |||
89 | return 0; | ||
90 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h new file mode 100644 index 00000000..51734b2f --- /dev/null +++ b/drivers/gpu/nvgpu/gm20b/fuse_gm20b.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * GM20B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GM20B_FUSE | ||
26 | #define _NVGPU_GM20B_FUSE | ||
27 | |||
28 | #define GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK ((u32)(1 << 0)) | ||
29 | #define GCPLEX_CONFIG_VPR_ENABLED_MASK ((u32)(1 << 1)) | ||
30 | #define GCPLEX_CONFIG_WPR_ENABLED_MASK ((u32)(1 << 2)) | ||
31 | |||
32 | |||
33 | struct gk20a; | ||
34 | |||
35 | int gm20b_fuse_check_priv_security(struct gk20a *g); | ||
36 | |||
37 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index bb18d2d7..779dde3d 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -54,6 +54,7 @@ | |||
54 | #include "bus_gm20b.h" | 54 | #include "bus_gm20b.h" |
55 | #include "hal_gm20b.h" | 55 | #include "hal_gm20b.h" |
56 | #include "acr_gm20b.h" | 56 | #include "acr_gm20b.h" |
57 | #include "fuse_gm20b.h" | ||
57 | 58 | ||
58 | #include <nvgpu/debug.h> | 59 | #include <nvgpu/debug.h> |
59 | #include <nvgpu/bug.h> | 60 | #include <nvgpu/bug.h> |
@@ -582,6 +583,9 @@ static const struct gpu_ops gm20b_ops = { | |||
582 | .priv_ring = { | 583 | .priv_ring = { |
583 | .isr = gk20a_priv_ring_isr, | 584 | .isr = gk20a_priv_ring_isr, |
584 | }, | 585 | }, |
586 | .fuse = { | ||
587 | .check_priv_security = gm20b_fuse_check_priv_security, | ||
588 | }, | ||
585 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, | 589 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, |
586 | .get_litter_value = gm20b_get_litter_value, | 590 | .get_litter_value = gm20b_get_litter_value, |
587 | }; | 591 | }; |
@@ -589,7 +593,6 @@ static const struct gpu_ops gm20b_ops = { | |||
589 | int gm20b_init_hal(struct gk20a *g) | 593 | int gm20b_init_hal(struct gk20a *g) |
590 | { | 594 | { |
591 | struct gpu_ops *gops = &g->ops; | 595 | struct gpu_ops *gops = &g->ops; |
592 | u32 val; | ||
593 | 596 | ||
594 | gops->ltc = gm20b_ops.ltc; | 597 | gops->ltc = gm20b_ops.ltc; |
595 | gops->ce2 = gm20b_ops.ce2; | 598 | gops->ce2 = gm20b_ops.ce2; |
@@ -625,26 +628,19 @@ int gm20b_init_hal(struct gk20a *g) | |||
625 | 628 | ||
626 | gops->priv_ring = gm20b_ops.priv_ring; | 629 | gops->priv_ring = gm20b_ops.priv_ring; |
627 | 630 | ||
631 | gops->fuse = gm20b_ops.fuse; | ||
632 | |||
628 | /* Lone functions */ | 633 | /* Lone functions */ |
629 | gops->chip_init_gpu_characteristics = | 634 | gops->chip_init_gpu_characteristics = |
630 | gm20b_ops.chip_init_gpu_characteristics; | 635 | gm20b_ops.chip_init_gpu_characteristics; |
631 | gops->get_litter_value = gm20b_ops.get_litter_value; | 636 | gops->get_litter_value = gm20b_ops.get_litter_value; |
632 | 637 | ||
633 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 638 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
634 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
635 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 639 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
636 | 640 | ||
637 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 641 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
638 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 642 | if (gops->fuse.check_priv_security(g)) |
639 | } else { | 643 | return -EINVAL; /* Do not boot gpu */ |
640 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
641 | if (!val) { | ||
642 | gk20a_dbg_info("priv security is disabled in HW"); | ||
643 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
644 | } else { | ||
645 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
646 | } | ||
647 | } | ||
648 | 644 | ||
649 | /* priv security dependent ops */ | 645 | /* priv security dependent ops */ |
650 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 646 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.c b/drivers/gpu/nvgpu/gp106/fuse_gp106.c new file mode 100644 index 00000000..68c0db89 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/fuse_gp106.c | |||
@@ -0,0 +1,35 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/enabled.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | |||
29 | int gp106_fuse_check_priv_security(struct gk20a *g) | ||
30 | { | ||
31 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
32 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
33 | |||
34 | return 0; | ||
35 | } | ||
diff --git a/drivers/gpu/nvgpu/gp106/fuse_gp106.h b/drivers/gpu/nvgpu/gp106/fuse_gp106.h new file mode 100644 index 00000000..dfb776b8 --- /dev/null +++ b/drivers/gpu/nvgpu/gp106/fuse_gp106.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GP106 FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GP106_FUSE | ||
26 | #define _NVGPU_GP106_FUSE | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | int gp106_fuse_check_priv_security(struct gk20a *g); | ||
31 | |||
32 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index e9ee77fc..d63398c7 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -79,6 +79,7 @@ | |||
79 | #include "gp106/fb_gp106.h" | 79 | #include "gp106/fb_gp106.h" |
80 | #include "gp106/gp106_gating_reglist.h" | 80 | #include "gp106/gp106_gating_reglist.h" |
81 | #include "gp106/flcn_gp106.h" | 81 | #include "gp106/flcn_gp106.h" |
82 | #include "gp106/fuse_gp106.h" | ||
82 | 83 | ||
83 | #include "hal_gp106.h" | 84 | #include "hal_gp106.h" |
84 | 85 | ||
@@ -704,6 +705,9 @@ static const struct gpu_ops gp106_ops = { | |||
704 | .priv_ring = { | 705 | .priv_ring = { |
705 | .isr = gp10b_priv_ring_isr, | 706 | .isr = gp10b_priv_ring_isr, |
706 | }, | 707 | }, |
708 | .fuse = { | ||
709 | .check_priv_security = gp106_fuse_check_priv_security, | ||
710 | }, | ||
707 | .get_litter_value = gp106_get_litter_value, | 711 | .get_litter_value = gp106_get_litter_value, |
708 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, | 712 | .chip_init_gpu_characteristics = gp106_init_gpu_characteristics, |
709 | }; | 713 | }; |
@@ -753,6 +757,7 @@ int gp106_init_hal(struct gk20a *g) | |||
753 | gops->xve = gp106_ops.xve; | 757 | gops->xve = gp106_ops.xve; |
754 | gops->falcon = gp106_ops.falcon; | 758 | gops->falcon = gp106_ops.falcon; |
755 | gops->priv_ring = gp106_ops.priv_ring; | 759 | gops->priv_ring = gp106_ops.priv_ring; |
760 | gops->fuse = gp106_ops.fuse; | ||
756 | 761 | ||
757 | /* Lone functions */ | 762 | /* Lone functions */ |
758 | gops->get_litter_value = gp106_ops.get_litter_value; | 763 | gops->get_litter_value = gp106_ops.get_litter_value; |
@@ -760,11 +765,13 @@ int gp106_init_hal(struct gk20a *g) | |||
760 | gp106_ops.chip_init_gpu_characteristics; | 765 | gp106_ops.chip_init_gpu_characteristics; |
761 | 766 | ||
762 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 767 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
763 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
764 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
765 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); | 768 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, true); |
766 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | 769 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); |
767 | 770 | ||
771 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ | ||
772 | if (gops->fuse.check_priv_security(g)) | ||
773 | return -EINVAL; /* Do not boot gpu */ | ||
774 | |||
768 | g->pmu_lsf_pmu_wpr_init_done = 0; | 775 | g->pmu_lsf_pmu_wpr_init_done = 0; |
769 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; | 776 | g->bootstrap_owner = LSF_FALCON_ID_SEC2; |
770 | 777 | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c new file mode 100644 index 00000000..7743c5df --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/types.h> | ||
26 | #include <nvgpu/fuse.h> | ||
27 | #include <nvgpu/enabled.h> | ||
28 | |||
29 | #include "gk20a/gk20a.h" | ||
30 | |||
31 | #include "gm20b/fuse_gm20b.h" | ||
32 | |||
33 | #include <nvgpu/hw/gp10b/hw_fuse_gp10b.h> | ||
34 | |||
35 | int gp10b_fuse_check_priv_security(struct gk20a *g) | ||
36 | { | ||
37 | u32 gcplex_config; | ||
38 | |||
39 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | ||
40 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
41 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
42 | nvgpu_log(g, gpu_dbg_info, "priv sec is disabled in fmodel"); | ||
43 | return 0; | ||
44 | } | ||
45 | |||
46 | if (nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &gcplex_config)) { | ||
47 | nvgpu_err(g, "err reading gcplex config fuse, check fuse clk"); | ||
48 | return -EINVAL; | ||
49 | } | ||
50 | |||
51 | if (gk20a_readl(g, fuse_opt_priv_sec_en_r())) { | ||
52 | /* | ||
53 | * all falcons have to boot in LS mode and this needs | ||
54 | * wpr_enabled set to 1 and vpr_auto_fetch_disable | ||
55 | * set to 0. In this case gmmu tries to pull wpr | ||
56 | * and vpr settings from tegra mc | ||
57 | */ | ||
58 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
59 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
60 | if ((gcplex_config & | ||
61 | GCPLEX_CONFIG_WPR_ENABLED_MASK) && | ||
62 | !(gcplex_config & | ||
63 | GCPLEX_CONFIG_VPR_AUTO_FETCH_DISABLE_MASK)) { | ||
64 | if (gk20a_readl(g, fuse_opt_sec_debug_en_r())) | ||
65 | nvgpu_log(g, gpu_dbg_info, | ||
66 | "gcplex_config = 0x%08x, " | ||
67 | "secure mode: ACR debug", | ||
68 | gcplex_config); | ||
69 | else | ||
70 | nvgpu_log(g, gpu_dbg_info, | ||
71 | "gcplex_config = 0x%08x, " | ||
72 | "secure mode: ACR non debug", | ||
73 | gcplex_config); | ||
74 | |||
75 | } else { | ||
76 | nvgpu_err(g, "gcplex_config = 0x%08x " | ||
77 | "invalid wpr_enabled/vpr_auto_fetch_disable " | ||
78 | "with priv_sec_en", gcplex_config); | ||
79 | /* do not try to boot GPU */ | ||
80 | return -EINVAL; | ||
81 | } | ||
82 | } else { | ||
83 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
84 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
85 | nvgpu_log(g, gpu_dbg_info, | ||
86 | "gcplex_config = 0x%08x, non secure mode", | ||
87 | gcplex_config); | ||
88 | } | ||
89 | |||
90 | return 0; | ||
91 | } | ||
diff --git a/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h new file mode 100644 index 00000000..1acb45d1 --- /dev/null +++ b/drivers/gpu/nvgpu/gp10b/fuse_gp10b.h | |||
@@ -0,0 +1,32 @@ | |||
1 | /* | ||
2 | * GP10B FUSE | ||
3 | * | ||
4 | * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef _NVGPU_GP10B_FUSE | ||
26 | #define _NVGPU_GP10B_FUSE | ||
27 | |||
28 | struct gk20a; | ||
29 | |||
30 | int gp10b_fuse_check_priv_security(struct gk20a *g); | ||
31 | |||
32 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 0b2a5712..335eb465 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -64,6 +64,7 @@ | |||
64 | 64 | ||
65 | #include "gp10b.h" | 65 | #include "gp10b.h" |
66 | #include "hal_gp10b.h" | 66 | #include "hal_gp10b.h" |
67 | #include "fuse_gp10b.h" | ||
67 | 68 | ||
68 | #include <nvgpu/debug.h> | 69 | #include <nvgpu/debug.h> |
69 | #include <nvgpu/bug.h> | 70 | #include <nvgpu/bug.h> |
@@ -619,6 +620,9 @@ static const struct gpu_ops gp10b_ops = { | |||
619 | .priv_ring = { | 620 | .priv_ring = { |
620 | .isr = gp10b_priv_ring_isr, | 621 | .isr = gp10b_priv_ring_isr, |
621 | }, | 622 | }, |
623 | .fuse = { | ||
624 | .check_priv_security = gp10b_fuse_check_priv_security, | ||
625 | }, | ||
622 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, | 626 | .chip_init_gpu_characteristics = gp10b_init_gpu_characteristics, |
623 | .get_litter_value = gp10b_get_litter_value, | 627 | .get_litter_value = gp10b_get_litter_value, |
624 | }; | 628 | }; |
@@ -626,7 +630,6 @@ static const struct gpu_ops gp10b_ops = { | |||
626 | int gp10b_init_hal(struct gk20a *g) | 630 | int gp10b_init_hal(struct gk20a *g) |
627 | { | 631 | { |
628 | struct gpu_ops *gops = &g->ops; | 632 | struct gpu_ops *gops = &g->ops; |
629 | u32 val; | ||
630 | 633 | ||
631 | gops->ltc = gp10b_ops.ltc; | 634 | gops->ltc = gp10b_ops.ltc; |
632 | gops->ce2 = gp10b_ops.ce2; | 635 | gops->ce2 = gp10b_ops.ce2; |
@@ -654,6 +657,8 @@ int gp10b_init_hal(struct gk20a *g) | |||
654 | 657 | ||
655 | gops->priv_ring = gp10b_ops.priv_ring; | 658 | gops->priv_ring = gp10b_ops.priv_ring; |
656 | 659 | ||
660 | gops->fuse = gp10b_ops.fuse; | ||
661 | |||
657 | /* Lone Functions */ | 662 | /* Lone Functions */ |
658 | gops->chip_init_gpu_characteristics = | 663 | gops->chip_init_gpu_characteristics = |
659 | gp10b_ops.chip_init_gpu_characteristics; | 664 | gp10b_ops.chip_init_gpu_characteristics; |
@@ -662,23 +667,9 @@ int gp10b_init_hal(struct gk20a *g) | |||
662 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 667 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
663 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 668 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
664 | 669 | ||
665 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 670 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
666 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | 671 | if (gops->fuse.check_priv_security(g)) |
667 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | 672 | return -EINVAL; /* Do not boot gpu */ |
668 | } else if (g->is_virtual) { | ||
669 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
670 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
671 | } else { | ||
672 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
673 | if (val) { | ||
674 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
675 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, true); | ||
676 | } else { | ||
677 | gk20a_dbg_info("priv security is disabled in HW"); | ||
678 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
679 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
680 | } | ||
681 | } | ||
682 | 673 | ||
683 | /* priv security dependent ops */ | 674 | /* priv security dependent ops */ |
684 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 675 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index fc059caa..8278d4e5 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -61,6 +61,7 @@ | |||
61 | #include "gp10b/mm_gp10b.h" | 61 | #include "gp10b/mm_gp10b.h" |
62 | #include "gp10b/pmu_gp10b.h" | 62 | #include "gp10b/pmu_gp10b.h" |
63 | #include "gp10b/gr_gp10b.h" | 63 | #include "gp10b/gr_gp10b.h" |
64 | #include "gp10b/fuse_gp10b.h" | ||
64 | 65 | ||
65 | #include "gp106/pmu_gp106.h" | 66 | #include "gp106/pmu_gp106.h" |
66 | #include "gp106/acr_gp106.h" | 67 | #include "gp106/acr_gp106.h" |
@@ -684,6 +685,9 @@ static const struct gpu_ops gv11b_ops = { | |||
684 | .priv_ring = { | 685 | .priv_ring = { |
685 | .isr = gp10b_priv_ring_isr, | 686 | .isr = gp10b_priv_ring_isr, |
686 | }, | 687 | }, |
688 | .fuse = { | ||
689 | .check_priv_security = gp10b_fuse_check_priv_security, | ||
690 | }, | ||
687 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, | 691 | .chip_init_gpu_characteristics = gv11b_init_gpu_characteristics, |
688 | .get_litter_value = gv11b_get_litter_value, | 692 | .get_litter_value = gv11b_get_litter_value, |
689 | }; | 693 | }; |
@@ -691,8 +695,6 @@ static const struct gpu_ops gv11b_ops = { | |||
691 | int gv11b_init_hal(struct gk20a *g) | 695 | int gv11b_init_hal(struct gk20a *g) |
692 | { | 696 | { |
693 | struct gpu_ops *gops = &g->ops; | 697 | struct gpu_ops *gops = &g->ops; |
694 | u32 val; | ||
695 | bool priv_security; | ||
696 | 698 | ||
697 | gops->ltc = gv11b_ops.ltc; | 699 | gops->ltc = gv11b_ops.ltc; |
698 | gops->ce2 = gv11b_ops.ce2; | 700 | gops->ce2 = gv11b_ops.ce2; |
@@ -717,23 +719,18 @@ int gv11b_init_hal(struct gk20a *g) | |||
717 | #endif | 719 | #endif |
718 | gops->falcon = gv11b_ops.falcon; | 720 | gops->falcon = gv11b_ops.falcon; |
719 | gops->priv_ring = gv11b_ops.priv_ring; | 721 | gops->priv_ring = gv11b_ops.priv_ring; |
722 | gops->fuse = gv11b_ops.fuse; | ||
720 | 723 | ||
721 | /* Lone functions */ | 724 | /* Lone functions */ |
722 | gops->chip_init_gpu_characteristics = | 725 | gops->chip_init_gpu_characteristics = |
723 | gv11b_ops.chip_init_gpu_characteristics; | 726 | gv11b_ops.chip_init_gpu_characteristics; |
724 | gops->get_litter_value = gv11b_ops.get_litter_value; | 727 | gops->get_litter_value = gv11b_ops.get_litter_value; |
725 | 728 | ||
726 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
727 | if (val) { | ||
728 | priv_security = true; | ||
729 | pr_err("priv security is enabled\n"); | ||
730 | } else { | ||
731 | priv_security = false; | ||
732 | pr_err("priv security is disabled\n"); | ||
733 | } | ||
734 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); | 729 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, false); |
735 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, priv_security); | 730 | |
736 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, priv_security); | 731 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
732 | if (gops->fuse.check_priv_security(g)) | ||
733 | return -EINVAL; /* Do not boot gpu */ | ||
737 | 734 | ||
738 | /* priv security dependent ops */ | 735 | /* priv security dependent ops */ |
739 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 736 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |