diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/regops_gk20a.c | 2 |
4 files changed, 27 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c index 4dee3faf..7b617a03 100644 --- a/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ctrl_gk20a.c | |||
@@ -243,6 +243,20 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g, | |||
243 | return err; | 243 | return err; |
244 | } | 244 | } |
245 | 245 | ||
246 | static int nvgpu_gpu_ioctl_l2_fb_ops(struct gk20a *g, | ||
247 | struct nvgpu_gpu_l2_fb_args *args) | ||
248 | { | ||
249 | int err = 0; | ||
250 | |||
251 | if (args->l2_flush) | ||
252 | g->ops.mm.l2_flush(g, args->l2_invalidate ? true : false); | ||
253 | |||
254 | if (args->fb_flush) | ||
255 | g->ops.mm.fb_flush(g); | ||
256 | |||
257 | return err; | ||
258 | } | ||
259 | |||
246 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) | 260 | long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg) |
247 | { | 261 | { |
248 | struct platform_device *dev = filp->private_data; | 262 | struct platform_device *dev = filp->private_data; |
@@ -423,6 +437,10 @@ long gk20a_ctrl_dev_ioctl(struct file *filp, unsigned int cmd, unsigned long arg | |||
423 | err = gk20a_channel_open_ioctl(g, | 437 | err = gk20a_channel_open_ioctl(g, |
424 | (struct nvgpu_channel_open_args *)buf); | 438 | (struct nvgpu_channel_open_args *)buf); |
425 | break; | 439 | break; |
440 | case NVGPU_GPU_IOCTL_FLUSH_L2: | ||
441 | err = nvgpu_gpu_ioctl_l2_fb_ops(g, | ||
442 | (struct nvgpu_gpu_l2_fb_args *)buf); | ||
443 | break; | ||
426 | default: | 444 | default: |
427 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); | 445 | dev_dbg(dev_from_gk20a(g), "unrecognized gpu ioctl cmd: 0x%x", cmd); |
428 | err = -ENOTTY; | 446 | err = -ENOTTY; |
diff --git a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c index 5bee34fc..ffb52549 100644 --- a/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/dbg_gpu_gk20a.c | |||
@@ -412,19 +412,16 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
412 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: | 412 | case NVGPU_DBG_GPU_IOCTL_BIND_CHANNEL: |
413 | err = dbg_bind_channel_gk20a(dbg_s, | 413 | err = dbg_bind_channel_gk20a(dbg_s, |
414 | (struct nvgpu_dbg_gpu_bind_channel_args *)buf); | 414 | (struct nvgpu_dbg_gpu_bind_channel_args *)buf); |
415 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
416 | break; | 415 | break; |
417 | 416 | ||
418 | case NVGPU_DBG_GPU_IOCTL_REG_OPS: | 417 | case NVGPU_DBG_GPU_IOCTL_REG_OPS: |
419 | err = nvgpu_ioctl_channel_reg_ops(dbg_s, | 418 | err = nvgpu_ioctl_channel_reg_ops(dbg_s, |
420 | (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); | 419 | (struct nvgpu_dbg_gpu_exec_reg_ops_args *)buf); |
421 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
422 | break; | 420 | break; |
423 | 421 | ||
424 | case NVGPU_DBG_GPU_IOCTL_POWERGATE: | 422 | case NVGPU_DBG_GPU_IOCTL_POWERGATE: |
425 | err = nvgpu_ioctl_powergate_gk20a(dbg_s, | 423 | err = nvgpu_ioctl_powergate_gk20a(dbg_s, |
426 | (struct nvgpu_dbg_gpu_powergate_args *)buf); | 424 | (struct nvgpu_dbg_gpu_powergate_args *)buf); |
427 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
428 | break; | 425 | break; |
429 | 426 | ||
430 | case NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL: | 427 | case NVGPU_DBG_GPU_IOCTL_EVENTS_CTRL: |
@@ -460,6 +457,8 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
460 | break; | 457 | break; |
461 | } | 458 | } |
462 | 459 | ||
460 | gk20a_dbg(gpu_dbg_gpu_dbg, "ret=%d", err); | ||
461 | |||
463 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) | 462 | if ((err == 0) && (_IOC_DIR(cmd) & _IOC_READ)) |
464 | err = copy_to_user((void __user *)arg, | 463 | err = copy_to_user((void __user *)arg, |
465 | buf, _IOC_SIZE(cmd)); | 464 | buf, _IOC_SIZE(cmd)); |
@@ -741,6 +740,8 @@ static int nvgpu_dbg_gpu_ioctl_suspend_resume_sm( | |||
741 | bool ch_is_curr_ctx; | 740 | bool ch_is_curr_ctx; |
742 | int err = 0, action = args->mode; | 741 | int err = 0, action = args->mode; |
743 | 742 | ||
743 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "action: %d", args->mode); | ||
744 | |||
744 | mutex_lock(&g->dbg_sessions_lock); | 745 | mutex_lock(&g->dbg_sessions_lock); |
745 | 746 | ||
746 | /* Suspend GPU context switching */ | 747 | /* Suspend GPU context switching */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 3115b5c3..ab3f18ba 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1502,7 +1502,7 @@ static int gr_gk20a_init_golden_ctx_image(struct gk20a *g, | |||
1502 | ctx_header_words = roundup(ctx_header_bytes, sizeof(u32)); | 1502 | ctx_header_words = roundup(ctx_header_bytes, sizeof(u32)); |
1503 | ctx_header_words >>= 2; | 1503 | ctx_header_words >>= 2; |
1504 | 1504 | ||
1505 | gk20a_mm_l2_flush(g, true); | 1505 | g->ops.mm.l2_flush(g, true); |
1506 | 1506 | ||
1507 | for (i = 0; i < ctx_header_words; i++) { | 1507 | for (i = 0; i < ctx_header_words; i++) { |
1508 | data = gk20a_mem_rd32(ctx_ptr, i); | 1508 | data = gk20a_mem_rd32(ctx_ptr, i); |
@@ -1565,7 +1565,7 @@ int gr_gk20a_update_smpc_ctxsw_mode(struct gk20a *g, | |||
1565 | 1565 | ||
1566 | /* Channel gr_ctx buffer is gpu cacheable. | 1566 | /* Channel gr_ctx buffer is gpu cacheable. |
1567 | Flush and invalidate before cpu update. */ | 1567 | Flush and invalidate before cpu update. */ |
1568 | gk20a_mm_l2_flush(g, true); | 1568 | g->ops.mm.l2_flush(g, true); |
1569 | 1569 | ||
1570 | ctx_ptr = vmap(ch_ctx->gr_ctx->pages, | 1570 | ctx_ptr = vmap(ch_ctx->gr_ctx->pages, |
1571 | PAGE_ALIGN(ch_ctx->gr_ctx->size) >> PAGE_SHIFT, | 1571 | PAGE_ALIGN(ch_ctx->gr_ctx->size) >> PAGE_SHIFT, |
@@ -1605,7 +1605,7 @@ int gr_gk20a_load_golden_ctx_image(struct gk20a *g, | |||
1605 | 1605 | ||
1606 | /* Channel gr_ctx buffer is gpu cacheable. | 1606 | /* Channel gr_ctx buffer is gpu cacheable. |
1607 | Flush and invalidate before cpu update. */ | 1607 | Flush and invalidate before cpu update. */ |
1608 | gk20a_mm_l2_flush(g, true); | 1608 | g->ops.mm.l2_flush(g, true); |
1609 | 1609 | ||
1610 | ctx_ptr = vmap(ch_ctx->gr_ctx->pages, | 1610 | ctx_ptr = vmap(ch_ctx->gr_ctx->pages, |
1611 | PAGE_ALIGN(ch_ctx->gr_ctx->size) >> PAGE_SHIFT, | 1611 | PAGE_ALIGN(ch_ctx->gr_ctx->size) >> PAGE_SHIFT, |
@@ -7003,7 +7003,7 @@ int gr_gk20a_exec_ctx_ops(struct channel_gk20a *ch, | |||
7003 | goto cleanup; | 7003 | goto cleanup; |
7004 | } | 7004 | } |
7005 | 7005 | ||
7006 | gk20a_mm_l2_flush(g, true); | 7006 | g->ops.mm.l2_flush(g, true); |
7007 | 7007 | ||
7008 | /* write to appropriate place in context image, | 7008 | /* write to appropriate place in context image, |
7009 | * first have to figure out where that really is */ | 7009 | * first have to figure out where that really is */ |
diff --git a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c index ceda48b3..b1c25ac9 100644 --- a/drivers/gpu/nvgpu/gk20a/regops_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/regops_gk20a.c | |||
@@ -697,7 +697,7 @@ static bool validate_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
697 | ok &= !err; | 697 | ok &= !err; |
698 | } | 698 | } |
699 | 699 | ||
700 | gk20a_dbg(gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d\n", | 700 | gk20a_dbg(gpu_dbg_gpu_dbg, "ctx_wrs:%d ctx_rds:%d", |
701 | *ctx_wr_count, *ctx_rd_count); | 701 | *ctx_wr_count, *ctx_rd_count); |
702 | 702 | ||
703 | return ok; | 703 | return ok; |