diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 9 |
5 files changed, 23 insertions, 15 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 7dd4a9fa..9203882c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -291,7 +291,8 @@ struct gpu_ops { | |||
291 | bool sm_debugger_attached, | 291 | bool sm_debugger_attached, |
292 | struct channel_gk20a *fault_ch, | 292 | struct channel_gk20a *fault_ch, |
293 | bool *early_exit, bool *ignore_debugger); | 293 | bool *early_exit, bool *ignore_debugger); |
294 | u32 (*mask_hww_warp_esr)(u32 hww_warp_esr); | 294 | u32 (*get_sm_hww_warp_esr)(struct gk20a *g, |
295 | u32 gpc, u32 tpc, u32 sm); | ||
295 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, | 296 | void (*get_esr_sm_sel)(struct gk20a *g, u32 gpc, u32 tpc, |
296 | u32 *esr_sm_sel); | 297 | u32 *esr_sm_sel); |
297 | int (*handle_sm_exception)(struct gk20a *g, | 298 | int (*handle_sm_exception)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 42a807f6..6fe330c0 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5518,11 +5518,6 @@ void gk20a_gr_clear_sm_hww(struct gk20a *g, | |||
5518 | gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f()); | 5518 | gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f()); |
5519 | } | 5519 | } |
5520 | 5520 | ||
5521 | u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr) | ||
5522 | { | ||
5523 | return hww_warp_esr; | ||
5524 | } | ||
5525 | |||
5526 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 5521 | int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
5527 | bool *post_event, struct channel_gk20a *fault_ch, | 5522 | bool *post_event, struct channel_gk20a *fault_ch, |
5528 | u32 *hww_global_esr) | 5523 | u32 *hww_global_esr) |
@@ -5549,8 +5544,7 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | |||
5549 | 5544 | ||
5550 | global_esr = gk20a_readl(g, | 5545 | global_esr = gk20a_readl(g, |
5551 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 5546 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
5552 | warp_esr = gk20a_readl(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | 5547 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); |
5553 | warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr); | ||
5554 | 5548 | ||
5555 | if (!sm_debugger_attached) { | 5549 | if (!sm_debugger_attached) { |
5556 | nvgpu_err(g, "sm hww global %08x warp %08x", | 5550 | nvgpu_err(g, "sm hww global %08x warp %08x", |
@@ -7941,6 +7935,8 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
7941 | u32 dbgr_status0 = 0, dbgr_control0 = 0; | 7935 | u32 dbgr_status0 = 0, dbgr_control0 = 0; |
7942 | u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; | 7936 | u64 warps_valid = 0, warps_paused = 0, warps_trapped = 0; |
7943 | struct nvgpu_timeout timeout; | 7937 | struct nvgpu_timeout timeout; |
7938 | u32 warp_esr; | ||
7939 | u32 sm = 0; | ||
7944 | 7940 | ||
7945 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | 7941 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, |
7946 | "GPC%d TPC%d: locking down SM", gpc, tpc); | 7942 | "GPC%d TPC%d: locking down SM", gpc, tpc); |
@@ -7952,12 +7948,10 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
7952 | do { | 7948 | do { |
7953 | u32 global_esr = gk20a_readl(g, | 7949 | u32 global_esr = gk20a_readl(g, |
7954 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | 7950 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); |
7955 | u32 warp_esr = gk20a_readl(g, | ||
7956 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | ||
7957 | dbgr_status0 = gk20a_readl(g, | 7951 | dbgr_status0 = gk20a_readl(g, |
7958 | gr_gpc0_tpc0_sm_dbgr_status0_r() + offset); | 7952 | gr_gpc0_tpc0_sm_dbgr_status0_r() + offset); |
7959 | 7953 | ||
7960 | warp_esr = g->ops.gr.mask_hww_warp_esr(warp_esr); | 7954 | warp_esr = g->ops.gr.get_sm_hww_warp_esr(g, gpc, tpc, sm); |
7961 | 7955 | ||
7962 | locked_down = | 7956 | locked_down = |
7963 | (gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(dbgr_status0) == | 7957 | (gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(dbgr_status0) == |
@@ -8496,3 +8490,11 @@ u32 gr_gk20a_tpc_enabled_exceptions(struct gk20a *g) | |||
8496 | 8490 | ||
8497 | return tpc_exception_en; | 8491 | return tpc_exception_en; |
8498 | } | 8492 | } |
8493 | |||
8494 | u32 gk20a_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm) | ||
8495 | { | ||
8496 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
8497 | u32 hww_warp_esr = gk20a_readl(g, | ||
8498 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | ||
8499 | return hww_warp_esr; | ||
8500 | } | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 5a28deea..924410c3 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -693,7 +693,7 @@ int gr_gk20a_get_ctx_id(struct gk20a *g, | |||
693 | struct channel_gk20a *c, | 693 | struct channel_gk20a *c, |
694 | u32 *ctx_id); | 694 | u32 *ctx_id); |
695 | 695 | ||
696 | u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr); | 696 | u32 gk20a_gr_get_sm_hww_warp_esr(struct gk20a *g, u32 gpc, u32 tpc, u32 sm); |
697 | 697 | ||
698 | int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, | 698 | int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long duration_ms, |
699 | u32 expect_delay); | 699 | u32 expect_delay); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 5fac9ac8..f3ba11b7 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1593,7 +1593,6 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1593 | gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info; | 1593 | gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info; |
1594 | gops->gr.get_access_map = gr_gm20b_get_access_map; | 1594 | gops->gr.get_access_map = gr_gm20b_get_access_map; |
1595 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; | 1595 | gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error; |
1596 | gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr; | ||
1597 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; | 1596 | gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception; |
1598 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; | 1597 | gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception; |
1599 | gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; | 1598 | gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions; |
@@ -1635,4 +1634,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; | 1634 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; |
1636 | gops->gr.resume_single_sm = gk20a_gr_resume_single_sm; | 1635 | gops->gr.resume_single_sm = gk20a_gr_resume_single_sm; |
1637 | gops->gr.resume_all_sms = gk20a_gr_resume_all_sms; | 1636 | gops->gr.resume_all_sms = gk20a_gr_resume_all_sms; |
1637 | gops->gr.get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr; | ||
1638 | } | 1638 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index e3ea4603..64ec5e1a 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1958,8 +1958,13 @@ clean_up: | |||
1958 | return gk20a_gr_handle_fecs_error(g, __ch, isr_data); | 1958 | return gk20a_gr_handle_fecs_error(g, __ch, isr_data); |
1959 | } | 1959 | } |
1960 | 1960 | ||
1961 | static u32 gp10b_mask_hww_warp_esr(u32 hww_warp_esr) | 1961 | static u32 gp10b_gr_get_sm_hww_warp_esr(struct gk20a *g, |
1962 | u32 gpc, u32 tpc, u32 sm) | ||
1962 | { | 1963 | { |
1964 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); | ||
1965 | u32 hww_warp_esr = gk20a_readl(g, | ||
1966 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | ||
1967 | |||
1963 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) | 1968 | if (!(hww_warp_esr & gr_gpc0_tpc0_sm_hww_warp_esr_addr_valid_m())) |
1964 | hww_warp_esr = set_field(hww_warp_esr, | 1969 | hww_warp_esr = set_field(hww_warp_esr, |
1965 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), | 1970 | gr_gpc0_tpc0_sm_hww_warp_esr_addr_error_type_m(), |
@@ -2369,7 +2374,6 @@ void gp10b_init_gr(struct gpu_ops *gops) | |||
2369 | gops->gr.get_access_map = gr_gp10b_get_access_map; | 2374 | gops->gr.get_access_map = gr_gp10b_get_access_map; |
2370 | gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; | 2375 | gops->gr.handle_sm_exception = gr_gp10b_handle_sm_exception; |
2371 | gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; | 2376 | gops->gr.handle_tex_exception = gr_gp10b_handle_tex_exception; |
2372 | gops->gr.mask_hww_warp_esr = gp10b_mask_hww_warp_esr; | ||
2373 | gops->gr.pre_process_sm_exception = | 2377 | gops->gr.pre_process_sm_exception = |
2374 | gr_gp10b_pre_process_sm_exception; | 2378 | gr_gp10b_pre_process_sm_exception; |
2375 | gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; | 2379 | gops->gr.handle_fecs_error = gr_gp10b_handle_fecs_error; |
@@ -2384,4 +2388,5 @@ void gp10b_init_gr(struct gpu_ops *gops) | |||
2384 | gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; | 2388 | gops->gr.set_boosted_ctx = gr_gp10b_set_boosted_ctx; |
2385 | gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; | 2389 | gops->gr.update_boosted_ctx = gr_gp10b_update_boosted_ctx; |
2386 | gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass; | 2390 | gops->gr.set_czf_bypass = gr_gp10b_set_czf_bypass; |
2391 | gops->gr.get_sm_hww_warp_esr = gp10b_gr_get_sm_hww_warp_esr; | ||
2387 | } | 2392 | } |