diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/fb/fb_gm20b.c | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 |
11 files changed, 27 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c index 5e78f636..56c7429a 100644 --- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c +++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c | |||
@@ -35,7 +35,6 @@ | |||
35 | 35 | ||
36 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> | 36 | #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> |
37 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> | 37 | #include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> |
38 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | ||
39 | 38 | ||
40 | #define VPR_INFO_FETCH_WAIT (5) | 39 | #define VPR_INFO_FETCH_WAIT (5) |
41 | #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c | 40 | #define WPR_INFO_ADDR_ALIGNMENT 0x0000000c |
@@ -209,15 +208,13 @@ bool gm20b_fb_debug_mode_enabled(struct gk20a *g) | |||
209 | 208 | ||
210 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | 209 | void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) |
211 | { | 210 | { |
212 | u32 reg_val, fb_debug_ctrl, gpc_debug_ctrl; | 211 | u32 reg_val, fb_debug_ctrl; |
213 | 212 | ||
214 | if (enable) { | 213 | if (enable) { |
215 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); | 214 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_enabled_f(); |
216 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
217 | g->mmu_debug_ctrl = true; | 215 | g->mmu_debug_ctrl = true; |
218 | } else { | 216 | } else { |
219 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); | 217 | fb_debug_ctrl = fb_mmu_debug_ctrl_debug_disabled_f(); |
220 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
221 | g->mmu_debug_ctrl = false; | 218 | g->mmu_debug_ctrl = false; |
222 | } | 219 | } |
223 | 220 | ||
@@ -226,8 +223,5 @@ void gm20b_fb_set_debug_mode(struct gk20a *g, bool enable) | |||
226 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); | 223 | fb_mmu_debug_ctrl_debug_m(), fb_debug_ctrl); |
227 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); | 224 | gk20a_writel(g, fb_mmu_debug_ctrl_r(), reg_val); |
228 | 225 | ||
229 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | 226 | g->ops.gr.set_debug_mode(g, enable); |
230 | reg_val = set_field(reg_val, | ||
231 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
232 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
233 | } | 227 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f62dfb94..f0b0bebe 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -509,6 +509,7 @@ struct gpu_ops { | |||
509 | enum ctxsw_addr_type addr_type, u32 num_tpcs, | 509 | enum ctxsw_addr_type addr_type, u32 num_tpcs, |
510 | u32 num_ppcs, u32 reg_list_ppc_count, | 510 | u32 num_ppcs, u32 reg_list_ppc_count, |
511 | u32 *__offset_in_segment); | 511 | u32 *__offset_in_segment); |
512 | void (*set_debug_mode)(struct gk20a *g, bool enable); | ||
512 | } gr; | 513 | } gr; |
513 | struct { | 514 | struct { |
514 | void (*init_hw)(struct gk20a *g); | 515 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 7ed36144..101f4211 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1516,3 +1516,19 @@ u32 gr_gm20b_get_pmm_per_chiplet_offset(void) | |||
1516 | { | 1516 | { |
1517 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); | 1517 | return (perf_pmmsys_extent_v() - perf_pmmsys_base_v() + 1); |
1518 | } | 1518 | } |
1519 | |||
1520 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable) | ||
1521 | { | ||
1522 | u32 reg_val, gpc_debug_ctrl; | ||
1523 | |||
1524 | if (enable) { | ||
1525 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_enabled_f(); | ||
1526 | } else { | ||
1527 | gpc_debug_ctrl = gr_gpcs_pri_mmu_debug_ctrl_debug_disabled_f(); | ||
1528 | } | ||
1529 | |||
1530 | reg_val = gk20a_readl(g, gr_gpcs_pri_mmu_debug_ctrl_r()); | ||
1531 | reg_val = set_field(reg_val, | ||
1532 | gr_gpcs_pri_mmu_debug_ctrl_debug_m(), gpc_debug_ctrl); | ||
1533 | gk20a_writel(g, gr_gpcs_pri_mmu_debug_ctrl_r(), reg_val); | ||
1534 | } | ||
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 7c3baa59..0f5dfe53 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -127,4 +127,5 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, | |||
127 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 127 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
128 | u32 global_esr); | 128 | u32 global_esr); |
129 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | 129 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); |
130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); | ||
130 | #endif | 131 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index a2b23cca..3b80ede0 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -329,6 +329,7 @@ static const struct gpu_ops gm20b_ops = { | |||
329 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, | 329 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, |
330 | .get_offset_in_gpccs_segment = | 330 | .get_offset_in_gpccs_segment = |
331 | gr_gk20a_get_offset_in_gpccs_segment, | 331 | gr_gk20a_get_offset_in_gpccs_segment, |
332 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
332 | }, | 333 | }, |
333 | .fb = { | 334 | .fb = { |
334 | .reset = fb_gk20a_reset, | 335 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 167bfaac..42ff647c 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -403,6 +403,7 @@ static const struct gpu_ops gp106_ops = { | |||
403 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, | 403 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, |
404 | .get_offset_in_gpccs_segment = | 404 | .get_offset_in_gpccs_segment = |
405 | gr_gk20a_get_offset_in_gpccs_segment, | 405 | gr_gk20a_get_offset_in_gpccs_segment, |
406 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
406 | }, | 407 | }, |
407 | .fb = { | 408 | .fb = { |
408 | .reset = gp106_fb_reset, | 409 | .reset = gp106_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index f4ae1314..9e42c6ba 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -365,6 +365,7 @@ static const struct gpu_ops gp10b_ops = { | |||
365 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, | 365 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, |
366 | .get_offset_in_gpccs_segment = | 366 | .get_offset_in_gpccs_segment = |
367 | gr_gk20a_get_offset_in_gpccs_segment, | 367 | gr_gk20a_get_offset_in_gpccs_segment, |
368 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
368 | }, | 369 | }, |
369 | .fb = { | 370 | .fb = { |
370 | .reset = fb_gk20a_reset, | 371 | .reset = fb_gk20a_reset, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 339d7813..0529fd91 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -459,6 +459,7 @@ static const struct gpu_ops gv100_ops = { | |||
459 | .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, | 459 | .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, |
460 | .get_offset_in_gpccs_segment = | 460 | .get_offset_in_gpccs_segment = |
461 | gr_gk20a_get_offset_in_gpccs_segment, | 461 | gr_gk20a_get_offset_in_gpccs_segment, |
462 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
462 | }, | 463 | }, |
463 | .fb = { | 464 | .fb = { |
464 | .reset = gv100_fb_reset, | 465 | .reset = gv100_fb_reset, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index ff9fc8c6..d87975d1 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -422,6 +422,7 @@ static const struct gpu_ops gv11b_ops = { | |||
422 | .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, | 422 | .get_nonpes_aware_tpc = gr_gv11b_get_nonpes_aware_tpc, |
423 | .get_offset_in_gpccs_segment = | 423 | .get_offset_in_gpccs_segment = |
424 | gr_gk20a_get_offset_in_gpccs_segment, | 424 | gr_gk20a_get_offset_in_gpccs_segment, |
425 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
425 | }, | 426 | }, |
426 | .fb = { | 427 | .fb = { |
427 | .reset = gv11b_fb_reset, | 428 | .reset = gv11b_fb_reset, |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 3aa9b092..fa8395eb 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -235,6 +235,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
235 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, | 235 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, |
236 | .get_offset_in_gpccs_segment = | 236 | .get_offset_in_gpccs_segment = |
237 | gr_gk20a_get_offset_in_gpccs_segment, | 237 | gr_gk20a_get_offset_in_gpccs_segment, |
238 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
238 | }, | 239 | }, |
239 | .fb = { | 240 | .fb = { |
240 | .reset = NULL, | 241 | .reset = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 44bcb123..66f25e24 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -272,6 +272,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
272 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, | 272 | .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers, |
273 | .get_offset_in_gpccs_segment = | 273 | .get_offset_in_gpccs_segment = |
274 | gr_gk20a_get_offset_in_gpccs_segment, | 274 | gr_gk20a_get_offset_in_gpccs_segment, |
275 | .set_debug_mode = gm20b_gr_set_debug_mode, | ||
275 | }, | 276 | }, |
276 | .fb = { | 277 | .fb = { |
277 | .reset = NULL, | 278 | .reset = NULL, |