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-rw-r--r--drivers/gpu/nvgpu/gv100/gr_gv100.c20
1 files changed, 0 insertions, 20 deletions
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index 0fa05714..bf143dbb 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -277,26 +277,6 @@ exit_build_table:
277 return err; 277 return err;
278} 278}
279 279
280void gr_gv100_load_tpc_mask(struct gk20a *g)
281{
282 u64 pes_tpc_mask = 0x0ULL;
283 u32 gpc, pes;
284 u32 num_tpc_per_gpc = nvgpu_get_litter_value(g,
285 GPU_LIT_NUM_TPC_PER_GPC);
286
287 /* gv100 has 6 GPC and 7 TPC/GPC */
288 for (gpc = 0; gpc < g->gr.gpc_count; gpc++) {
289 for (pes = 0; pes < g->gr.pe_count_per_gpc; pes++) {
290 pes_tpc_mask |= (u64) g->gr.pes_tpc_mask[pes][gpc] <<
291 (num_tpc_per_gpc * gpc);
292 }
293 }
294
295 nvgpu_log_info(g, "pes_tpc_mask: %016llx\n", pes_tpc_mask);
296 gk20a_writel(g, gr_fe_tpc_fs_r(0), u64_lo32(pes_tpc_mask));
297 gk20a_writel(g, gr_fe_tpc_fs_r(1), u64_hi32(pes_tpc_mask));
298}
299
300u32 gr_gv100_get_patch_slots(struct gk20a *g) 280u32 gr_gv100_get_patch_slots(struct gk20a *g)
301{ 281{
302 struct gr_gk20a *gr = &g->gr; 282 struct gr_gk20a *gr = &g->gr;