diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 80 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 90 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 77 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 1 |
13 files changed, 0 insertions, 263 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 200f58a3..368c9321 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1306,22 +1306,6 @@ static void gm20b_gr_read_sm_error_state(struct gk20a *g, | |||
1306 | 1306 | ||
1307 | } | 1307 | } |
1308 | 1308 | ||
1309 | static void gm20b_gr_write_sm_error_state(struct gk20a *g, | ||
1310 | u32 offset, | ||
1311 | struct nvgpu_tsg_sm_error_state *sm_error_states) | ||
1312 | { | ||
1313 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_global_esr_r() + offset, | ||
1314 | sm_error_states->hww_global_esr); | ||
1315 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset, | ||
1316 | sm_error_states->hww_warp_esr); | ||
1317 | gk20a_writel(g, gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset, | ||
1318 | u64_lo32(sm_error_states->hww_warp_esr_pc)); | ||
1319 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset, | ||
1320 | sm_error_states->hww_global_esr_report_mask); | ||
1321 | gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset, | ||
1322 | sm_error_states->hww_warp_esr_report_mask); | ||
1323 | } | ||
1324 | |||
1325 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 1309 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
1326 | struct channel_gk20a *fault_ch) | 1310 | struct channel_gk20a *fault_ch) |
1327 | { | 1311 | { |
@@ -1356,70 +1340,6 @@ record_fail: | |||
1356 | return sm_id; | 1340 | return sm_id; |
1357 | } | 1341 | } |
1358 | 1342 | ||
1359 | int gm20b_gr_update_sm_error_state(struct gk20a *g, | ||
1360 | struct channel_gk20a *ch, u32 sm_id, | ||
1361 | struct nvgpu_tsg_sm_error_state *sm_error_state) | ||
1362 | { | ||
1363 | u32 gpc, tpc, offset; | ||
1364 | struct tsg_gk20a *tsg; | ||
1365 | struct nvgpu_gr_ctx *ch_ctx; | ||
1366 | struct nvgpu_tsg_sm_error_state *tsg_sm_error_states; | ||
1367 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
1368 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, | ||
1369 | GPU_LIT_TPC_IN_GPC_STRIDE); | ||
1370 | int err = 0; | ||
1371 | |||
1372 | tsg = tsg_gk20a_from_ch(ch); | ||
1373 | if (!tsg) { | ||
1374 | return -EINVAL; | ||
1375 | } | ||
1376 | |||
1377 | ch_ctx = &tsg->gr_ctx; | ||
1378 | |||
1379 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
1380 | |||
1381 | tsg_sm_error_states = tsg->sm_error_states + sm_id; | ||
1382 | gk20a_tsg_update_sm_error_state_locked(tsg, sm_id, sm_error_state); | ||
1383 | |||
1384 | err = gr_gk20a_disable_ctxsw(g); | ||
1385 | if (err) { | ||
1386 | nvgpu_err(g, "unable to stop gr ctxsw"); | ||
1387 | goto fail; | ||
1388 | } | ||
1389 | |||
1390 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | ||
1391 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | ||
1392 | |||
1393 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
1394 | |||
1395 | if (gk20a_is_channel_ctx_resident(ch)) { | ||
1396 | gm20b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); | ||
1397 | } else { | ||
1398 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | ||
1399 | if (err) { | ||
1400 | goto enable_ctxsw; | ||
1401 | } | ||
1402 | |||
1403 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
1404 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset, | ||
1405 | tsg_sm_error_states->hww_global_esr_report_mask, | ||
1406 | true); | ||
1407 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
1408 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset, | ||
1409 | tsg_sm_error_states->hww_warp_esr_report_mask, | ||
1410 | true); | ||
1411 | |||
1412 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); | ||
1413 | } | ||
1414 | |||
1415 | enable_ctxsw: | ||
1416 | err = gr_gk20a_enable_ctxsw(g); | ||
1417 | |||
1418 | fail: | ||
1419 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
1420 | return err; | ||
1421 | } | ||
1422 | |||
1423 | int gm20b_gr_clear_sm_error_state(struct gk20a *g, | 1343 | int gm20b_gr_clear_sm_error_state(struct gk20a *g, |
1424 | struct channel_gk20a *ch, u32 sm_id) | 1344 | struct channel_gk20a *ch, u32 sm_id) |
1425 | { | 1345 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 0a486c2e..7402478d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -117,9 +117,6 @@ void gr_gm20b_get_access_map(struct gk20a *g, | |||
117 | u32 **whitelist, int *num_entries); | 117 | u32 **whitelist, int *num_entries); |
118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, | 118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, |
119 | u32 tpc, u32 sm, struct channel_gk20a *fault_ch); | 119 | u32 tpc, u32 sm, struct channel_gk20a *fault_ch); |
120 | int gm20b_gr_update_sm_error_state(struct gk20a *g, | ||
121 | struct channel_gk20a *ch, u32 sm_id, | ||
122 | struct nvgpu_tsg_sm_error_state *sm_error_state); | ||
123 | int gm20b_gr_clear_sm_error_state(struct gk20a *g, | 120 | int gm20b_gr_clear_sm_error_state(struct gk20a *g, |
124 | struct channel_gk20a *ch, u32 sm_id); | 121 | struct channel_gk20a *ch, u32 sm_id); |
125 | int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, | 122 | int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 772a4a85..114d259a 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -275,7 +275,6 @@ static const struct gpu_ops gm20b_ops = { | |||
275 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 275 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
276 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 276 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
277 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 277 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
278 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
279 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 278 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
280 | .suspend_contexts = gr_gk20a_suspend_contexts, | 279 | .suspend_contexts = gr_gk20a_suspend_contexts, |
281 | .resume_contexts = gr_gk20a_resume_contexts, | 280 | .resume_contexts = gr_gk20a_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index a1682c79..ef66be56 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -338,7 +338,6 @@ static const struct gpu_ops gp106_ops = { | |||
338 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 338 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
339 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 339 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
340 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 340 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
341 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
342 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 341 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
343 | .suspend_contexts = gr_gp10b_suspend_contexts, | 342 | .suspend_contexts = gr_gp10b_suspend_contexts, |
344 | .resume_contexts = gr_gk20a_resume_contexts, | 343 | .resume_contexts = gr_gk20a_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index a524a551..769cab74 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -295,7 +295,6 @@ static const struct gpu_ops gp10b_ops = { | |||
295 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 295 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
296 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 296 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
297 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 297 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
298 | .update_sm_error_state = gm20b_gr_update_sm_error_state, | ||
299 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 298 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
300 | .suspend_contexts = gr_gp10b_suspend_contexts, | 299 | .suspend_contexts = gr_gp10b_suspend_contexts, |
301 | .resume_contexts = gr_gk20a_resume_contexts, | 300 | .resume_contexts = gr_gk20a_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index d6ee0139..ee6dd436 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -377,7 +377,6 @@ static const struct gpu_ops gv100_ops = { | |||
377 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 377 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
378 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, | 378 | .init_hwpm_pmm_register = gr_gv100_init_hwpm_pmm_register, |
379 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 379 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
380 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
381 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 380 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
382 | .suspend_contexts = gr_gp10b_suspend_contexts, | 381 | .suspend_contexts = gr_gp10b_suspend_contexts, |
383 | .resume_contexts = gr_gk20a_resume_contexts, | 382 | .resume_contexts = gr_gk20a_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 78cb1b98..3dedc6b5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -3228,96 +3228,6 @@ void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) | |||
3228 | } | 3228 | } |
3229 | } | 3229 | } |
3230 | 3230 | ||
3231 | static void gv11b_gr_write_sm_error_state(struct gk20a *g, | ||
3232 | u32 offset, | ||
3233 | struct nvgpu_tsg_sm_error_state *sm_error_states) | ||
3234 | { | ||
3235 | nvgpu_writel(g, | ||
3236 | gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
3237 | sm_error_states->hww_global_esr); | ||
3238 | nvgpu_writel(g, | ||
3239 | gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, | ||
3240 | sm_error_states->hww_warp_esr); | ||
3241 | nvgpu_writel(g, | ||
3242 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_r() + offset, | ||
3243 | u64_lo32(sm_error_states->hww_warp_esr_pc)); | ||
3244 | nvgpu_writel(g, | ||
3245 | gr_gpc0_tpc0_sm0_hww_warp_esr_pc_hi_r() + offset, | ||
3246 | u64_hi32(sm_error_states->hww_warp_esr_pc)); | ||
3247 | nvgpu_writel(g, | ||
3248 | gr_gpc0_tpc0_sm0_hww_global_esr_report_mask_r() + offset, | ||
3249 | sm_error_states->hww_global_esr_report_mask); | ||
3250 | nvgpu_writel(g, | ||
3251 | gr_gpc0_tpc0_sm0_hww_warp_esr_report_mask_r() + offset, | ||
3252 | sm_error_states->hww_warp_esr_report_mask); | ||
3253 | } | ||
3254 | |||
3255 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | ||
3256 | struct channel_gk20a *ch, u32 sm_id, | ||
3257 | struct nvgpu_tsg_sm_error_state *sm_error_state) | ||
3258 | { | ||
3259 | struct tsg_gk20a *tsg; | ||
3260 | u32 gpc, tpc, sm, offset; | ||
3261 | struct nvgpu_gr_ctx *ch_ctx; | ||
3262 | int err = 0; | ||
3263 | struct nvgpu_tsg_sm_error_state *tsg_sm_error_states; | ||
3264 | |||
3265 | tsg = tsg_gk20a_from_ch(ch); | ||
3266 | if (tsg == NULL) { | ||
3267 | return -EINVAL; | ||
3268 | } | ||
3269 | |||
3270 | ch_ctx = &tsg->gr_ctx; | ||
3271 | |||
3272 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
3273 | |||
3274 | tsg_sm_error_states = tsg->sm_error_states + sm_id; | ||
3275 | gk20a_tsg_update_sm_error_state_locked(tsg, sm_id, sm_error_state); | ||
3276 | |||
3277 | err = gr_gk20a_disable_ctxsw(g); | ||
3278 | if (err) { | ||
3279 | nvgpu_err(g, "unable to stop gr ctxsw"); | ||
3280 | goto fail; | ||
3281 | } | ||
3282 | |||
3283 | gpc = g->gr.sm_to_cluster[sm_id].gpc_index; | ||
3284 | tpc = g->gr.sm_to_cluster[sm_id].tpc_index; | ||
3285 | sm = g->gr.sm_to_cluster[sm_id].sm_index; | ||
3286 | |||
3287 | offset = gk20a_gr_gpc_offset(g, gpc) + | ||
3288 | gk20a_gr_tpc_offset(g, tpc) + | ||
3289 | gv11b_gr_sm_offset(g, sm); | ||
3290 | |||
3291 | if (gk20a_is_channel_ctx_resident(ch)) { | ||
3292 | gv11b_gr_write_sm_error_state(g, offset, tsg_sm_error_states); | ||
3293 | } else { | ||
3294 | err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false); | ||
3295 | if (err) { | ||
3296 | goto enable_ctxsw; | ||
3297 | } | ||
3298 | |||
3299 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3300 | gr_gpcs_tpcs_sms_hww_global_esr_report_mask_r() + | ||
3301 | offset, | ||
3302 | tsg_sm_error_states->hww_global_esr_report_mask, | ||
3303 | true); | ||
3304 | gr_gk20a_ctx_patch_write(g, ch_ctx, | ||
3305 | gr_gpcs_tpcs_sms_hww_warp_esr_report_mask_r() + | ||
3306 | offset, | ||
3307 | tsg_sm_error_states->hww_warp_esr_report_mask, | ||
3308 | true); | ||
3309 | |||
3310 | gr_gk20a_ctx_patch_write_end(g, ch_ctx, false); | ||
3311 | } | ||
3312 | |||
3313 | enable_ctxsw: | ||
3314 | err = gr_gk20a_enable_ctxsw(g); | ||
3315 | |||
3316 | fail: | ||
3317 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
3318 | return err; | ||
3319 | } | ||
3320 | |||
3321 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 3231 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
3322 | struct channel_gk20a *ch, u64 sms, bool enable) | 3232 | struct channel_gk20a *ch, u64 sms, bool enable) |
3323 | { | 3233 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index a4b8fa91..20377acf 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -166,9 +166,6 @@ void gv11b_gr_get_esr_sm_sel(struct gk20a *g, u32 gpc, u32 tpc, | |||
166 | u32 *esr_sm_sel); | 166 | u32 *esr_sm_sel); |
167 | int gv11b_gr_sm_trigger_suspend(struct gk20a *g); | 167 | int gv11b_gr_sm_trigger_suspend(struct gk20a *g); |
168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); | 168 | void gv11b_gr_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); |
169 | int gv11b_gr_update_sm_error_state(struct gk20a *g, | ||
170 | struct channel_gk20a *ch, u32 sm_id, | ||
171 | struct nvgpu_tsg_sm_error_state *sm_error_state); | ||
172 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, | 169 | int gv11b_gr_set_sm_debug_mode(struct gk20a *g, |
173 | struct channel_gk20a *ch, u64 sms, bool enable); | 170 | struct channel_gk20a *ch, u64 sms, bool enable); |
174 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 171 | int gv11b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 479b06d1..591a7786 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -329,7 +329,6 @@ static const struct gpu_ops gv11b_ops = { | |||
329 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, | 329 | .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode, |
330 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, | 330 | .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode, |
331 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 331 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
332 | .update_sm_error_state = gv11b_gr_update_sm_error_state, | ||
333 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, | 332 | .clear_sm_error_state = gm20b_gr_clear_sm_error_state, |
334 | .suspend_contexts = gr_gp10b_suspend_contexts, | 333 | .suspend_contexts = gr_gp10b_suspend_contexts, |
335 | .resume_contexts = gr_gk20a_resume_contexts, | 334 | .resume_contexts = gr_gk20a_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h index 1ca6be0d..8f2881ec 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h +++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h | |||
@@ -397,9 +397,6 @@ struct gpu_ops { | |||
397 | u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); | 397 | u32 (*get_lrf_tex_ltc_dram_override)(struct gk20a *g); |
398 | int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc, | 398 | int (*record_sm_error_state)(struct gk20a *g, u32 gpc, u32 tpc, |
399 | u32 sm, struct channel_gk20a *fault_ch); | 399 | u32 sm, struct channel_gk20a *fault_ch); |
400 | int (*update_sm_error_state)(struct gk20a *g, | ||
401 | struct channel_gk20a *ch, u32 sm_id, | ||
402 | struct nvgpu_tsg_sm_error_state *sm_error_state); | ||
403 | int (*clear_sm_error_state)(struct gk20a *g, | 400 | int (*clear_sm_error_state)(struct gk20a *g, |
404 | struct channel_gk20a *ch, u32 sm_id); | 401 | struct channel_gk20a *ch, u32 sm_id); |
405 | int (*suspend_contexts)(struct gk20a *g, | 402 | int (*suspend_contexts)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index 1eace94b..953b7168 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -260,78 +260,6 @@ static int nvgpu_dbg_gpu_ioctl_timeout(struct dbg_session_gk20a *dbg_s, | |||
260 | return err; | 260 | return err; |
261 | } | 261 | } |
262 | 262 | ||
263 | static int nvgpu_dbg_gpu_ioctl_write_single_sm_error_state( | ||
264 | struct dbg_session_gk20a *dbg_s, | ||
265 | struct nvgpu_dbg_gpu_write_single_sm_error_state_args *args) | ||
266 | { | ||
267 | struct gk20a *g = dbg_s->g; | ||
268 | struct gr_gk20a *gr = &g->gr; | ||
269 | u32 sm_id; | ||
270 | struct channel_gk20a *ch; | ||
271 | struct nvgpu_dbg_gpu_sm_error_state_record sm_error_state_record; | ||
272 | struct nvgpu_tsg_sm_error_state sm_error_state; | ||
273 | int err = 0; | ||
274 | |||
275 | /* Not currently supported in the virtual case */ | ||
276 | if (g->is_virtual) { | ||
277 | return -ENOSYS; | ||
278 | } | ||
279 | |||
280 | ch = nvgpu_dbg_gpu_get_session_channel(dbg_s); | ||
281 | if (ch == NULL) { | ||
282 | return -EINVAL; | ||
283 | } | ||
284 | |||
285 | sm_id = args->sm_id; | ||
286 | if (sm_id >= gr->no_of_sm) { | ||
287 | return -EINVAL; | ||
288 | } | ||
289 | |||
290 | nvgpu_speculation_barrier(); | ||
291 | |||
292 | if (args->sm_error_state_record_size > 0) { | ||
293 | size_t read_size = sizeof(sm_error_state_record); | ||
294 | |||
295 | if (read_size > args->sm_error_state_record_size) | ||
296 | read_size = args->sm_error_state_record_size; | ||
297 | |||
298 | nvgpu_mutex_acquire(&g->dbg_sessions_lock); | ||
299 | err = copy_from_user(&sm_error_state_record, | ||
300 | (void __user *)(uintptr_t) | ||
301 | args->sm_error_state_record_mem, | ||
302 | read_size); | ||
303 | nvgpu_mutex_release(&g->dbg_sessions_lock); | ||
304 | if (err != 0) { | ||
305 | return -ENOMEM; | ||
306 | } | ||
307 | } | ||
308 | |||
309 | err = gk20a_busy(g); | ||
310 | if (err != 0) { | ||
311 | return err; | ||
312 | } | ||
313 | |||
314 | sm_error_state.hww_global_esr = | ||
315 | sm_error_state_record.hww_global_esr; | ||
316 | sm_error_state.hww_warp_esr = | ||
317 | sm_error_state_record.hww_warp_esr; | ||
318 | sm_error_state.hww_warp_esr_pc = | ||
319 | sm_error_state_record.hww_warp_esr_pc; | ||
320 | sm_error_state.hww_global_esr_report_mask = | ||
321 | sm_error_state_record.hww_global_esr_report_mask; | ||
322 | sm_error_state.hww_warp_esr_report_mask = | ||
323 | sm_error_state_record.hww_warp_esr_report_mask; | ||
324 | |||
325 | err = gr_gk20a_elpg_protected_call(g, | ||
326 | g->ops.gr.update_sm_error_state(g, ch, | ||
327 | sm_id, &sm_error_state)); | ||
328 | |||
329 | gk20a_idle(g); | ||
330 | |||
331 | return err; | ||
332 | } | ||
333 | |||
334 | |||
335 | static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( | 263 | static int nvgpu_dbg_gpu_ioctl_read_single_sm_error_state( |
336 | struct dbg_session_gk20a *dbg_s, | 264 | struct dbg_session_gk20a *dbg_s, |
337 | struct nvgpu_dbg_gpu_read_single_sm_error_state_args *args) | 265 | struct nvgpu_dbg_gpu_read_single_sm_error_state_args *args) |
@@ -2066,11 +1994,6 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd, | |||
2066 | (struct nvgpu_dbg_gpu_clear_single_sm_error_state_args *)buf); | 1994 | (struct nvgpu_dbg_gpu_clear_single_sm_error_state_args *)buf); |
2067 | break; | 1995 | break; |
2068 | 1996 | ||
2069 | case NVGPU_DBG_GPU_IOCTL_WRITE_SINGLE_SM_ERROR_STATE: | ||
2070 | err = nvgpu_dbg_gpu_ioctl_write_single_sm_error_state(dbg_s, | ||
2071 | (struct nvgpu_dbg_gpu_write_single_sm_error_state_args *)buf); | ||
2072 | break; | ||
2073 | |||
2074 | case NVGPU_DBG_GPU_IOCTL_UNBIND_CHANNEL: | 1997 | case NVGPU_DBG_GPU_IOCTL_UNBIND_CHANNEL: |
2075 | err = dbg_unbind_channel_gk20a(dbg_s, | 1998 | err = dbg_unbind_channel_gk20a(dbg_s, |
2076 | (struct nvgpu_dbg_gpu_unbind_channel_args *)buf); | 1999 | (struct nvgpu_dbg_gpu_unbind_channel_args *)buf); |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index a90d2d94..2ec08ae6 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -168,7 +168,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
168 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | 168 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, |
169 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 169 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
170 | .record_sm_error_state = gm20b_gr_record_sm_error_state, | 170 | .record_sm_error_state = gm20b_gr_record_sm_error_state, |
171 | .update_sm_error_state = NULL, | ||
172 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 171 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
173 | .suspend_contexts = vgpu_gr_suspend_contexts, | 172 | .suspend_contexts = vgpu_gr_suspend_contexts, |
174 | .resume_contexts = vgpu_gr_resume_contexts, | 173 | .resume_contexts = vgpu_gr_resume_contexts, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 3a917bf3..eac57433 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -185,7 +185,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
185 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, | 185 | .update_smpc_ctxsw_mode = vgpu_gr_update_smpc_ctxsw_mode, |
186 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, | 186 | .update_hwpm_ctxsw_mode = vgpu_gr_update_hwpm_ctxsw_mode, |
187 | .record_sm_error_state = gv11b_gr_record_sm_error_state, | 187 | .record_sm_error_state = gv11b_gr_record_sm_error_state, |
188 | .update_sm_error_state = NULL, | ||
189 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, | 188 | .clear_sm_error_state = vgpu_gr_clear_sm_error_state, |
190 | .suspend_contexts = vgpu_gr_suspend_contexts, | 189 | .suspend_contexts = vgpu_gr_suspend_contexts, |
191 | .resume_contexts = vgpu_gr_resume_contexts, | 190 | .resume_contexts = vgpu_gr_resume_contexts, |