diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_common.c | 155 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | 135 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/ltc_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | 121 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | 10 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | 35 |
6 files changed, 291 insertions, 169 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_common.c b/drivers/gpu/nvgpu/gk20a/ltc_common.c deleted file mode 100644 index 2b015fa0..00000000 --- a/drivers/gpu/nvgpu/gk20a/ltc_common.c +++ /dev/null | |||
@@ -1,155 +0,0 @@ | |||
1 | /* | ||
2 | * drivers/video/tegra/host/gk20a/ltc_common.c | ||
3 | * | ||
4 | * GK20A Graphics | ||
5 | * | ||
6 | * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved. | ||
7 | * | ||
8 | * This program is free software; you can redistribute it and/or modify it | ||
9 | * under the terms and conditions of the GNU General Public License, | ||
10 | * version 2, as published by the Free Software Foundation. | ||
11 | * | ||
12 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
15 | * more details. | ||
16 | * | ||
17 | * You should have received a copy of the GNU General Public License | ||
18 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | ||
19 | */ | ||
20 | |||
21 | #include <nvgpu/dma.h> | ||
22 | #include <nvgpu/enabled.h> | ||
23 | |||
24 | #include "gk20a.h" | ||
25 | #include "gr_gk20a.h" | ||
26 | |||
27 | /* | ||
28 | * Sets the ZBC color for the passed index. | ||
29 | */ | ||
30 | static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, | ||
31 | struct zbc_entry *color_val, | ||
32 | u32 index) | ||
33 | { | ||
34 | u32 i; | ||
35 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
36 | |||
37 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
38 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
39 | |||
40 | for (i = 0; | ||
41 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { | ||
42 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | ||
43 | color_val->color_l2[i]); | ||
44 | } | ||
45 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
46 | } | ||
47 | |||
48 | /* | ||
49 | * Sets the ZBC depth for the passed index. | ||
50 | */ | ||
51 | static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
52 | struct zbc_entry *depth_val, | ||
53 | u32 index) | ||
54 | { | ||
55 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
56 | |||
57 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
58 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
59 | |||
60 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | ||
61 | depth_val->depth); | ||
62 | |||
63 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
64 | } | ||
65 | |||
66 | static int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, | ||
67 | size_t compbit_backing_size) | ||
68 | { | ||
69 | struct gr_gk20a *gr = &g->gr; | ||
70 | |||
71 | return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_FORCE_CONTIGUOUS, | ||
72 | compbit_backing_size, | ||
73 | &gr->compbit_store.mem); | ||
74 | } | ||
75 | |||
76 | static int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, | ||
77 | size_t compbit_backing_size) | ||
78 | { | ||
79 | struct gr_gk20a *gr = &g->gr; | ||
80 | |||
81 | return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, | ||
82 | compbit_backing_size, | ||
83 | &gr->compbit_store.mem); | ||
84 | } | ||
85 | |||
86 | static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | ||
87 | { | ||
88 | u32 max_size = gr->max_comptag_mem; | ||
89 | u32 max_comptag_lines = max_size << 3; | ||
90 | |||
91 | u32 compbit_base_post_divide; | ||
92 | u64 compbit_base_post_multiply64; | ||
93 | u64 compbit_store_iova; | ||
94 | u64 compbit_base_post_divide64; | ||
95 | |||
96 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
97 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | ||
98 | else | ||
99 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | ||
100 | gr->compbit_store.mem.priv.sgt->sgl, 0); | ||
101 | |||
102 | compbit_base_post_divide64 = compbit_store_iova >> | ||
103 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
104 | |||
105 | do_div(compbit_base_post_divide64, g->ltc_count); | ||
106 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); | ||
107 | |||
108 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * | ||
109 | g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
110 | |||
111 | if (compbit_base_post_multiply64 < compbit_store_iova) | ||
112 | compbit_base_post_divide++; | ||
113 | |||
114 | /* Bug 1477079 indicates sw adjustment on the posted divided base. */ | ||
115 | if (g->ops.ltc.cbc_fix_config) | ||
116 | compbit_base_post_divide = | ||
117 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); | ||
118 | |||
119 | gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), | ||
120 | compbit_base_post_divide); | ||
121 | |||
122 | gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, | ||
123 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", | ||
124 | (u32)(compbit_store_iova >> 32), | ||
125 | (u32)(compbit_store_iova & 0xffffffff), | ||
126 | compbit_base_post_divide); | ||
127 | |||
128 | gr->compbit_store.base_hw = compbit_base_post_divide; | ||
129 | |||
130 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, | ||
131 | 0, max_comptag_lines - 1); | ||
132 | |||
133 | } | ||
134 | |||
135 | #ifdef CONFIG_DEBUG_FS | ||
136 | static void gk20a_ltc_sync_debugfs(struct gk20a *g) | ||
137 | { | ||
138 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | ||
139 | |||
140 | nvgpu_spinlock_acquire(&g->debugfs_lock); | ||
141 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | ||
142 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
143 | if (g->mm.ltc_enabled_debug) | ||
144 | /* bypass disabled (normal caching ops)*/ | ||
145 | reg &= ~reg_f; | ||
146 | else | ||
147 | /* bypass enabled (no caching) */ | ||
148 | reg |= reg_f; | ||
149 | |||
150 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | ||
151 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
152 | } | ||
153 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
154 | } | ||
155 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c index 8867202f..1d517c27 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.c | |||
@@ -21,14 +21,36 @@ | |||
21 | #include <nvgpu/log.h> | 21 | #include <nvgpu/log.h> |
22 | #include <nvgpu/bug.h> | 22 | #include <nvgpu/bug.h> |
23 | #include <nvgpu/enabled.h> | 23 | #include <nvgpu/enabled.h> |
24 | #include <nvgpu/dma.h> | ||
24 | 25 | ||
25 | #include "gk20a.h" | 26 | #include "gk20a.h" |
27 | #include "gr_gk20a.h" | ||
26 | #include "ltc_gk20a.h" | 28 | #include "ltc_gk20a.h" |
27 | 29 | ||
28 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> | 30 | #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h> |
29 | 31 | ||
30 | #include "ltc_common.c" | ||
31 | 32 | ||
33 | /* Non HW reg dependent stuff: */ | ||
34 | |||
35 | int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size) | ||
36 | { | ||
37 | struct gr_gk20a *gr = &g->gr; | ||
38 | |||
39 | return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_FORCE_CONTIGUOUS, | ||
40 | compbit_backing_size, | ||
41 | &gr->compbit_store.mem); | ||
42 | } | ||
43 | |||
44 | int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size) | ||
45 | { | ||
46 | struct gr_gk20a *gr = &g->gr; | ||
47 | |||
48 | return nvgpu_dma_alloc_flags_sys(g, NVGPU_DMA_NO_KERNEL_MAPPING, | ||
49 | compbit_backing_size, | ||
50 | &gr->compbit_store.mem); | ||
51 | } | ||
52 | |||
53 | /* HW reg dependent stuff: */ | ||
32 | static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | 54 | static int gk20a_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) |
33 | { | 55 | { |
34 | /* max memory size (MB) to cover */ | 56 | /* max memory size (MB) to cover */ |
@@ -231,6 +253,117 @@ static int gk20a_determine_L2_size_bytes(struct gk20a *g) | |||
231 | return cache_size; | 253 | return cache_size; |
232 | } | 254 | } |
233 | 255 | ||
256 | /* | ||
257 | * Sets the ZBC color for the passed index. | ||
258 | */ | ||
259 | static void gk20a_ltc_set_zbc_color_entry(struct gk20a *g, | ||
260 | struct zbc_entry *color_val, | ||
261 | u32 index) | ||
262 | { | ||
263 | u32 i; | ||
264 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
265 | |||
266 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
267 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
268 | |||
269 | for (i = 0; | ||
270 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { | ||
271 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | ||
272 | color_val->color_l2[i]); | ||
273 | } | ||
274 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
275 | } | ||
276 | |||
277 | /* | ||
278 | * Sets the ZBC depth for the passed index. | ||
279 | */ | ||
280 | static void gk20a_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
281 | struct zbc_entry *depth_val, | ||
282 | u32 index) | ||
283 | { | ||
284 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
285 | |||
286 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
287 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
288 | |||
289 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | ||
290 | depth_val->depth); | ||
291 | |||
292 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
293 | } | ||
294 | |||
295 | static void gk20a_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | ||
296 | { | ||
297 | u32 max_size = gr->max_comptag_mem; | ||
298 | u32 max_comptag_lines = max_size << 3; | ||
299 | |||
300 | u32 compbit_base_post_divide; | ||
301 | u64 compbit_base_post_multiply64; | ||
302 | u64 compbit_store_iova; | ||
303 | u64 compbit_base_post_divide64; | ||
304 | |||
305 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
306 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | ||
307 | else | ||
308 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | ||
309 | gr->compbit_store.mem.priv.sgt->sgl, 0); | ||
310 | |||
311 | compbit_base_post_divide64 = compbit_store_iova >> | ||
312 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
313 | |||
314 | do_div(compbit_base_post_divide64, g->ltc_count); | ||
315 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); | ||
316 | |||
317 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * | ||
318 | g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
319 | |||
320 | if (compbit_base_post_multiply64 < compbit_store_iova) | ||
321 | compbit_base_post_divide++; | ||
322 | |||
323 | /* Bug 1477079 indicates sw adjustment on the posted divided base. */ | ||
324 | if (g->ops.ltc.cbc_fix_config) | ||
325 | compbit_base_post_divide = | ||
326 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); | ||
327 | |||
328 | gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), | ||
329 | compbit_base_post_divide); | ||
330 | |||
331 | gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, | ||
332 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", | ||
333 | (u32)(compbit_store_iova >> 32), | ||
334 | (u32)(compbit_store_iova & 0xffffffff), | ||
335 | compbit_base_post_divide); | ||
336 | |||
337 | gr->compbit_store.base_hw = compbit_base_post_divide; | ||
338 | |||
339 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, | ||
340 | 0, max_comptag_lines - 1); | ||
341 | |||
342 | } | ||
343 | |||
344 | #ifdef CONFIG_DEBUG_FS | ||
345 | static void gk20a_ltc_sync_debugfs(struct gk20a *g) | ||
346 | { | ||
347 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | ||
348 | |||
349 | nvgpu_spinlock_acquire(&g->debugfs_lock); | ||
350 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | ||
351 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
352 | |||
353 | if (g->mm.ltc_enabled_debug) | ||
354 | /* bypass disabled (normal caching ops)*/ | ||
355 | reg &= ~reg_f; | ||
356 | else | ||
357 | /* bypass enabled (no caching) */ | ||
358 | reg |= reg_f; | ||
359 | |||
360 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | ||
361 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
362 | } | ||
363 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
364 | } | ||
365 | #endif | ||
366 | |||
234 | void gk20a_init_ltc(struct gpu_ops *gops) | 367 | void gk20a_init_ltc(struct gpu_ops *gops) |
235 | { | 368 | { |
236 | gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; | 369 | gops->ltc.determine_L2_size_bytes = gk20a_determine_L2_size_bytes; |
diff --git a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h index 3cace0fd..30d4163f 100644 --- a/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/ltc_gk20a.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A L2 | 2 | * GK20A L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -18,4 +18,6 @@ | |||
18 | struct gpu_ops; | 18 | struct gpu_ops; |
19 | 19 | ||
20 | void gk20a_init_ltc(struct gpu_ops *gops); | 20 | void gk20a_init_ltc(struct gpu_ops *gops); |
21 | int gk20a_ltc_alloc_phys_cbc(struct gk20a *g, size_t compbit_backing_size); | ||
22 | int gk20a_ltc_alloc_virt_cbc(struct gk20a *g, size_t compbit_backing_size); | ||
21 | #endif | 23 | #endif |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c index 791cc45b..e4e385fb 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c | |||
@@ -26,7 +26,7 @@ | |||
26 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | 26 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> |
27 | #include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h> | 27 | #include <nvgpu/hw/gm20b/hw_pri_ringmaster_gm20b.h> |
28 | 28 | ||
29 | #include "gk20a/ltc_common.c" | 29 | #include "gk20a/ltc_gk20a.h" |
30 | #include "ltc_gm20b.h" | 30 | #include "ltc_gm20b.h" |
31 | 31 | ||
32 | static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) | 32 | static int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr) |
@@ -349,13 +349,124 @@ static int gm20b_determine_L2_size_bytes(struct gk20a *g) | |||
349 | return cache_size; | 349 | return cache_size; |
350 | } | 350 | } |
351 | 351 | ||
352 | /* | ||
353 | * Sets the ZBC color for the passed index. | ||
354 | */ | ||
355 | void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, | ||
356 | struct zbc_entry *color_val, | ||
357 | u32 index) | ||
358 | { | ||
359 | u32 i; | ||
360 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
361 | |||
362 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
363 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
364 | |||
365 | for (i = 0; | ||
366 | i < ltc_ltcs_ltss_dstg_zbc_color_clear_value__size_1_v(); i++) { | ||
367 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_color_clear_value_r(i), | ||
368 | color_val->color_l2[i]); | ||
369 | } | ||
370 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
371 | } | ||
372 | |||
373 | /* | ||
374 | * Sets the ZBC depth for the passed index. | ||
375 | */ | ||
376 | void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
377 | struct zbc_entry *depth_val, | ||
378 | u32 index) | ||
379 | { | ||
380 | u32 real_index = index + GK20A_STARTOF_ZBC_TABLE; | ||
381 | |||
382 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_index_r(), | ||
383 | ltc_ltcs_ltss_dstg_zbc_index_address_f(real_index)); | ||
384 | |||
385 | gk20a_writel(g, ltc_ltcs_ltss_dstg_zbc_depth_clear_value_r(), | ||
386 | depth_val->depth); | ||
387 | |||
388 | gk20a_readl(g, ltc_ltcs_ltss_dstg_zbc_index_r()); | ||
389 | } | ||
390 | |||
391 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr) | ||
392 | { | ||
393 | u32 max_size = gr->max_comptag_mem; | ||
394 | u32 max_comptag_lines = max_size << 3; | ||
395 | |||
396 | u32 compbit_base_post_divide; | ||
397 | u64 compbit_base_post_multiply64; | ||
398 | u64 compbit_store_iova; | ||
399 | u64 compbit_base_post_divide64; | ||
400 | |||
401 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) | ||
402 | compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem); | ||
403 | else | ||
404 | compbit_store_iova = g->ops.mm.get_iova_addr(g, | ||
405 | gr->compbit_store.mem.priv.sgt->sgl, 0); | ||
406 | |||
407 | compbit_base_post_divide64 = compbit_store_iova >> | ||
408 | ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
409 | |||
410 | do_div(compbit_base_post_divide64, g->ltc_count); | ||
411 | compbit_base_post_divide = u64_lo32(compbit_base_post_divide64); | ||
412 | |||
413 | compbit_base_post_multiply64 = ((u64)compbit_base_post_divide * | ||
414 | g->ltc_count) << ltc_ltcs_ltss_cbc_base_alignment_shift_v(); | ||
415 | |||
416 | if (compbit_base_post_multiply64 < compbit_store_iova) | ||
417 | compbit_base_post_divide++; | ||
418 | |||
419 | /* Bug 1477079 indicates sw adjustment on the posted divided base. */ | ||
420 | if (g->ops.ltc.cbc_fix_config) | ||
421 | compbit_base_post_divide = | ||
422 | g->ops.ltc.cbc_fix_config(g, compbit_base_post_divide); | ||
423 | |||
424 | gk20a_writel(g, ltc_ltcs_ltss_cbc_base_r(), | ||
425 | compbit_base_post_divide); | ||
426 | |||
427 | gk20a_dbg(gpu_dbg_info | gpu_dbg_map_v | gpu_dbg_pte, | ||
428 | "compbit base.pa: 0x%x,%08x cbc_base:0x%08x\n", | ||
429 | (u32)(compbit_store_iova >> 32), | ||
430 | (u32)(compbit_store_iova & 0xffffffff), | ||
431 | compbit_base_post_divide); | ||
432 | |||
433 | gr->compbit_store.base_hw = compbit_base_post_divide; | ||
434 | |||
435 | g->ops.ltc.cbc_ctrl(g, gk20a_cbc_op_invalidate, | ||
436 | 0, max_comptag_lines - 1); | ||
437 | |||
438 | } | ||
439 | |||
440 | #ifdef CONFIG_DEBUG_FS | ||
441 | static void gm20b_ltc_sync_debugfs(struct gk20a *g) | ||
442 | { | ||
443 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | ||
444 | |||
445 | nvgpu_spinlock_acquire(&g->debugfs_lock); | ||
446 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | ||
447 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
448 | |||
449 | if (g->mm.ltc_enabled_debug) | ||
450 | /* bypass disabled (normal caching ops)*/ | ||
451 | reg &= ~reg_f; | ||
452 | else | ||
453 | /* bypass enabled (no caching) */ | ||
454 | reg |= reg_f; | ||
455 | |||
456 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | ||
457 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
458 | } | ||
459 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
460 | } | ||
461 | #endif | ||
462 | |||
352 | void gm20b_init_ltc(struct gpu_ops *gops) | 463 | void gm20b_init_ltc(struct gpu_ops *gops) |
353 | { | 464 | { |
354 | /* Gk20a reused ops. */ | 465 | /* Gk20a reused ops. */ |
355 | gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; | 466 | gops->ltc.determine_L2_size_bytes = gm20b_determine_L2_size_bytes; |
356 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | 467 | gops->ltc.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry; |
357 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | 468 | gops->ltc.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry; |
358 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | 469 | gops->ltc.init_cbc = gm20b_ltc_init_cbc; |
359 | 470 | ||
360 | /* GM20b specific ops. */ | 471 | /* GM20b specific ops. */ |
361 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; | 472 | gops->ltc.init_fs_state = gm20b_ltc_init_fs_state; |
@@ -365,6 +476,6 @@ void gm20b_init_ltc(struct gpu_ops *gops) | |||
365 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; | 476 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; |
366 | gops->ltc.flush = gm20b_flush_ltc; | 477 | gops->ltc.flush = gm20b_flush_ltc; |
367 | #ifdef CONFIG_DEBUG_FS | 478 | #ifdef CONFIG_DEBUG_FS |
368 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; | 479 | gops->ltc.sync_debugfs = gm20b_ltc_sync_debugfs; |
369 | #endif | 480 | #endif |
370 | } | 481 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h index fcd263de..4fe83250 100644 --- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B L2 | 2 | * GM20B L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -17,6 +17,14 @@ | |||
17 | #define _NVHOST_GM20B_LTC | 17 | #define _NVHOST_GM20B_LTC |
18 | struct gpu_ops; | 18 | struct gpu_ops; |
19 | 19 | ||
20 | void gm20b_ltc_set_zbc_color_entry(struct gk20a *g, | ||
21 | struct zbc_entry *color_val, | ||
22 | u32 index); | ||
23 | void gm20b_ltc_set_zbc_depth_entry(struct gk20a *g, | ||
24 | struct zbc_entry *depth_val, | ||
25 | u32 index); | ||
26 | void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr); | ||
27 | |||
20 | void gm20b_init_ltc(struct gpu_ops *gops); | 28 | void gm20b_init_ltc(struct gpu_ops *gops); |
21 | void gm20b_ltc_init_fs_state(struct gk20a *g); | 29 | void gm20b_ltc_init_fs_state(struct gk20a *g); |
22 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, | 30 | int gm20b_ltc_cbc_ctrl(struct gk20a *g, enum gk20a_cbc_op op, |
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c index b3026059..d94e56ce 100644 --- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GP10B L2 | 2 | * GP10B L2 |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -24,7 +24,7 @@ | |||
24 | #include <nvgpu/hw/gp10b/hw_mc_gp10b.h> | 24 | #include <nvgpu/hw/gp10b/hw_mc_gp10b.h> |
25 | #include <nvgpu/hw/gp10b/hw_ltc_gp10b.h> | 25 | #include <nvgpu/hw/gp10b/hw_ltc_gp10b.h> |
26 | 26 | ||
27 | #include "gk20a/ltc_common.c" | 27 | #include "gk20a/ltc_gk20a.h" |
28 | #include "ltc_gp10b.h" | 28 | #include "ltc_gp10b.h" |
29 | 29 | ||
30 | static int gp10b_determine_L2_size_bytes(struct gk20a *g) | 30 | static int gp10b_determine_L2_size_bytes(struct gk20a *g) |
@@ -205,12 +205,35 @@ static void gp10b_ltc_init_fs_state(struct gk20a *g) | |||
205 | ltc_intr); | 205 | ltc_intr); |
206 | } | 206 | } |
207 | 207 | ||
208 | #ifdef CONFIG_DEBUG_FS | ||
209 | static void gp10b_ltc_sync_debugfs(struct gk20a *g) | ||
210 | { | ||
211 | u32 reg_f = ltc_ltcs_ltss_tstg_set_mgmt_2_l2_bypass_mode_enabled_f(); | ||
212 | |||
213 | nvgpu_spinlock_acquire(&g->debugfs_lock); | ||
214 | if (g->mm.ltc_enabled != g->mm.ltc_enabled_debug) { | ||
215 | u32 reg = gk20a_readl(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r()); | ||
216 | |||
217 | if (g->mm.ltc_enabled_debug) | ||
218 | /* bypass disabled (normal caching ops)*/ | ||
219 | reg &= ~reg_f; | ||
220 | else | ||
221 | /* bypass enabled (no caching) */ | ||
222 | reg |= reg_f; | ||
223 | |||
224 | gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg); | ||
225 | g->mm.ltc_enabled = g->mm.ltc_enabled_debug; | ||
226 | } | ||
227 | nvgpu_spinlock_release(&g->debugfs_lock); | ||
228 | } | ||
229 | #endif | ||
230 | |||
208 | void gp10b_init_ltc(struct gpu_ops *gops) | 231 | void gp10b_init_ltc(struct gpu_ops *gops) |
209 | { | 232 | { |
210 | gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; | 233 | gops->ltc.determine_L2_size_bytes = gp10b_determine_L2_size_bytes; |
211 | gops->ltc.set_zbc_color_entry = gk20a_ltc_set_zbc_color_entry; | 234 | gops->ltc.set_zbc_color_entry = gm20b_ltc_set_zbc_color_entry; |
212 | gops->ltc.set_zbc_depth_entry = gk20a_ltc_set_zbc_depth_entry; | 235 | gops->ltc.set_zbc_depth_entry = gm20b_ltc_set_zbc_depth_entry; |
213 | gops->ltc.init_cbc = gk20a_ltc_init_cbc; | 236 | gops->ltc.init_cbc = gm20b_ltc_init_cbc; |
214 | 237 | ||
215 | /* GM20b specific ops. */ | 238 | /* GM20b specific ops. */ |
216 | gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; | 239 | gops->ltc.init_fs_state = gp10b_ltc_init_fs_state; |
@@ -220,6 +243,6 @@ void gp10b_init_ltc(struct gpu_ops *gops) | |||
220 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; | 243 | gops->ltc.cbc_fix_config = gm20b_ltc_cbc_fix_config; |
221 | gops->ltc.flush = gm20b_flush_ltc; | 244 | gops->ltc.flush = gm20b_flush_ltc; |
222 | #ifdef CONFIG_DEBUG_FS | 245 | #ifdef CONFIG_DEBUG_FS |
223 | gops->ltc.sync_debugfs = gk20a_ltc_sync_debugfs; | 246 | gops->ltc.sync_debugfs = gp10b_ltc_sync_debugfs; |
224 | #endif | 247 | #endif |
225 | } | 248 | } |