diff options
Diffstat (limited to 'drivers/gpu')
25 files changed, 168 insertions, 108 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 86e56d9e..0395e463 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -81,7 +81,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) | |||
81 | 81 | ||
82 | if (!enable) { | 82 | if (!enable) { |
83 | if (!g->ops.pmu.is_engine_in_reset(g)) { | 83 | if (!g->ops.pmu.is_engine_in_reset(g)) { |
84 | pmu_enable_irq(pmu, false); | 84 | g->ops.pmu.pmu_enable_irq(pmu, false); |
85 | pmu_enable_hw(pmu, false); | 85 | pmu_enable_hw(pmu, false); |
86 | } | 86 | } |
87 | } else { | 87 | } else { |
@@ -95,7 +95,7 @@ static int pmu_enable(struct nvgpu_pmu *pmu, bool enable) | |||
95 | goto exit; | 95 | goto exit; |
96 | } | 96 | } |
97 | 97 | ||
98 | pmu_enable_irq(pmu, true); | 98 | g->ops.pmu.pmu_enable_irq(pmu, true); |
99 | } | 99 | } |
100 | 100 | ||
101 | exit: | 101 | exit: |
@@ -412,7 +412,7 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
412 | if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { | 412 | if (nvgpu_is_enabled(g, NVGPU_PMU_ZBC_SAVE)) { |
413 | /* Save zbc table after PMU is initialized. */ | 413 | /* Save zbc table after PMU is initialized. */ |
414 | pmu->zbc_ready = true; | 414 | pmu->zbc_ready = true; |
415 | gk20a_pmu_save_zbc(g, 0xf); | 415 | g->ops.gr.pmu_save_zbc(g, 0xf); |
416 | } | 416 | } |
417 | 417 | ||
418 | if (g->elpg_enabled) { | 418 | if (g->elpg_enabled) { |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c index 6ad82ca8..68a39432 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_debug.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_debug.c | |||
@@ -39,7 +39,7 @@ void nvgpu_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu) | |||
39 | pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS], | 39 | pmu->stat_dmem_offset[PMU_PG_ELPG_ENGINE_ID_GRAPHICS], |
40 | sizeof(struct pmu_pg_stats_v2)); | 40 | sizeof(struct pmu_pg_stats_v2)); |
41 | 41 | ||
42 | gk20a_pmu_dump_elpg_stats(pmu); | 42 | g->ops.pmu.pmu_dump_elpg_stats(pmu); |
43 | } | 43 | } |
44 | 44 | ||
45 | void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | 45 | void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) |
@@ -47,7 +47,7 @@ void nvgpu_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu) | |||
47 | struct gk20a *g = pmu->g; | 47 | struct gk20a *g = pmu->g; |
48 | 48 | ||
49 | nvgpu_flcn_dump_stats(pmu->flcn); | 49 | nvgpu_flcn_dump_stats(pmu->flcn); |
50 | gk20a_pmu_dump_falcon_stats(pmu); | 50 | g->ops.pmu.pmu_dump_falcon_stats(pmu); |
51 | 51 | ||
52 | nvgpu_err(g, "pmu state: %d", pmu->pmu_state); | 52 | nvgpu_err(g, "pmu state: %d", pmu->pmu_state); |
53 | nvgpu_err(g, "elpg state: %d", pmu->elpg_stat); | 53 | nvgpu_err(g, "elpg state: %d", pmu->elpg_stat); |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c index 843a4551..9fe999ae 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_ipc.c | |||
@@ -744,8 +744,8 @@ int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | |||
744 | return 0; | 744 | return 0; |
745 | } | 745 | } |
746 | 746 | ||
747 | if (gk20a_pmu_is_interrupted(pmu)) { | 747 | if (g->ops.pmu.pmu_is_interrupted(pmu)) { |
748 | gk20a_pmu_isr(g); | 748 | g->ops.pmu.pmu_isr(g); |
749 | } | 749 | } |
750 | 750 | ||
751 | nvgpu_usleep_range(delay, delay * 2U); | 751 | nvgpu_usleep_range(delay, delay * 2U); |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c index 5d736591..a99e86ce 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_perfmon.c | |||
@@ -73,7 +73,7 @@ int nvgpu_pmu_init_perfmon(struct nvgpu_pmu *pmu) | |||
73 | 73 | ||
74 | pmu->perfmon_ready = 0; | 74 | pmu->perfmon_ready = 0; |
75 | 75 | ||
76 | gk20a_pmu_init_perfmon_counter(g); | 76 | g->ops.pmu.pmu_init_perfmon_counter(g); |
77 | 77 | ||
78 | if (!pmu->sample_buffer) { | 78 | if (!pmu->sample_buffer) { |
79 | pmu->sample_buffer = nvgpu_alloc(&pmu->dmem, | 79 | pmu->sample_buffer = nvgpu_alloc(&pmu->dmem, |
@@ -246,8 +246,8 @@ void nvgpu_pmu_get_load_counters(struct gk20a *g, u32 *busy_cycles, | |||
246 | return; | 246 | return; |
247 | } | 247 | } |
248 | 248 | ||
249 | *busy_cycles = gk20a_pmu_read_idle_counter(g, 1); | 249 | *busy_cycles = g->ops.pmu.pmu_read_idle_counter(g, 1); |
250 | *total_cycles = gk20a_pmu_read_idle_counter(g, 2); | 250 | *total_cycles = g->ops.pmu.pmu_read_idle_counter(g, 2); |
251 | 251 | ||
252 | gk20a_idle(g); | 252 | gk20a_idle(g); |
253 | } | 253 | } |
@@ -258,8 +258,8 @@ void nvgpu_pmu_reset_load_counters(struct gk20a *g) | |||
258 | return; | 258 | return; |
259 | } | 259 | } |
260 | 260 | ||
261 | gk20a_pmu_reset_idle_counter(g, 2); | 261 | g->ops.pmu.pmu_reset_idle_counter(g, 2); |
262 | gk20a_pmu_reset_idle_counter(g, 1); | 262 | g->ops.pmu.pmu_reset_idle_counter(g, 1); |
263 | 263 | ||
264 | gk20a_idle(g); | 264 | gk20a_idle(g); |
265 | } | 265 | } |
@@ -316,7 +316,7 @@ int nvgpu_pmu_init_perfmon_rpc(struct nvgpu_pmu *pmu) | |||
316 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perfmon_init)); | 316 | memset(&rpc, 0, sizeof(struct nv_pmu_rpc_struct_perfmon_init)); |
317 | pmu->perfmon_ready = 0; | 317 | pmu->perfmon_ready = 0; |
318 | 318 | ||
319 | gk20a_pmu_init_perfmon_counter(g); | 319 | g->ops.pmu.pmu_init_perfmon_counter(g); |
320 | 320 | ||
321 | /* microseconds interval between pmu polls perf counters */ | 321 | /* microseconds interval between pmu polls perf counters */ |
322 | rpc.sample_periodus = 16700; | 322 | rpc.sample_periodus = 16700; |
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c index 76ed0621..0758279d 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu_pg.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu_pg.c | |||
@@ -394,7 +394,7 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
394 | 394 | ||
395 | nvgpu_log_fn(g, " "); | 395 | nvgpu_log_fn(g, " "); |
396 | 396 | ||
397 | gk20a_pmu_pg_idle_counter_config(g, pg_engine_id); | 397 | g->ops.pmu.pmu_pg_idle_counter_config(g, pg_engine_id); |
398 | 398 | ||
399 | if (g->ops.pmu.pmu_pg_init_param) { | 399 | if (g->ops.pmu.pmu_pg_init_param) { |
400 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); | 400 | g->ops.pmu.pmu_pg_init_param(g, pg_engine_id); |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 192f4c3e..5a888303 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -68,7 +68,6 @@ struct nvgpu_ctxsw_trace_filter; | |||
68 | #include "ce2_gk20a.h" | 68 | #include "ce2_gk20a.h" |
69 | #include "fifo_gk20a.h" | 69 | #include "fifo_gk20a.h" |
70 | #include "tsg_gk20a.h" | 70 | #include "tsg_gk20a.h" |
71 | #include "pmu_gk20a.h" | ||
72 | #include "clk/clk.h" | 71 | #include "clk/clk.h" |
73 | #include "perf/perf.h" | 72 | #include "perf/perf.h" |
74 | #include "pmgr/pmgr.h" | 73 | #include "pmgr/pmgr.h" |
@@ -1025,6 +1024,15 @@ struct gpu_ops { | |||
1025 | u32 id, u32 *token); | 1024 | u32 id, u32 *token); |
1026 | int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, | 1025 | int (*pmu_mutex_release)(struct nvgpu_pmu *pmu, |
1027 | u32 id, u32 *token); | 1026 | u32 id, u32 *token); |
1027 | bool (*pmu_is_interrupted)(struct nvgpu_pmu *pmu); | ||
1028 | void (*pmu_isr)(struct gk20a *g); | ||
1029 | void (*pmu_init_perfmon_counter)(struct gk20a *g); | ||
1030 | void (*pmu_pg_idle_counter_config)(struct gk20a *g, u32 pg_engine_id); | ||
1031 | u32 (*pmu_read_idle_counter)(struct gk20a *g, u32 counter_id); | ||
1032 | void (*pmu_reset_idle_counter)(struct gk20a *g, u32 counter_id); | ||
1033 | void (*pmu_dump_elpg_stats)(struct nvgpu_pmu *pmu); | ||
1034 | void (*pmu_dump_falcon_stats)(struct nvgpu_pmu *pmu); | ||
1035 | void (*pmu_enable_irq)(struct nvgpu_pmu *pmu, bool enable); | ||
1028 | int (*init_wpr_region)(struct gk20a *g); | 1036 | int (*init_wpr_region)(struct gk20a *g); |
1029 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); | 1037 | int (*load_lsfalcon_ucode)(struct gk20a *g, u32 falconidmask); |
1030 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); | 1038 | void (*write_dmatrfbase)(struct gk20a *g, u32 addr); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index cdc00bbd..d4c461af 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3763,7 +3763,7 @@ void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | |||
3763 | } | 3763 | } |
3764 | 3764 | ||
3765 | /* update zbc */ | 3765 | /* update zbc */ |
3766 | gk20a_pmu_save_zbc(g, entries); | 3766 | g->ops.gr.pmu_save_zbc(g, entries); |
3767 | 3767 | ||
3768 | clean_up: | 3768 | clean_up: |
3769 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | 3769 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index a0eae127..f7631a9c 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -67,7 +67,7 @@ void mc_gk20a_isr_stall(struct gk20a *g) | |||
67 | gk20a_fifo_isr(g); | 67 | gk20a_fifo_isr(g); |
68 | } | 68 | } |
69 | if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { | 69 | if ((mc_intr_0 & mc_intr_0_pmu_pending_f()) != 0U) { |
70 | gk20a_pmu_isr(g); | 70 | g->ops.pmu.pmu_isr(g); |
71 | } | 71 | } |
72 | if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { | 72 | if ((mc_intr_0 & mc_intr_0_priv_ring_pending_f()) != 0U) { |
73 | g->ops.priv_ring.isr(g); | 73 | g->ops.priv_ring.isr(g); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 9ec4c867..64e4a567 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -37,6 +37,7 @@ | |||
37 | 37 | ||
38 | #include "gk20a.h" | 38 | #include "gk20a.h" |
39 | #include "gr_gk20a.h" | 39 | #include "gr_gk20a.h" |
40 | #include "pmu_gk20a.h" | ||
40 | 41 | ||
41 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> | 42 | #include <nvgpu/hw/gk20a/hw_mc_gk20a.h> |
42 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> | 43 | #include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> |
@@ -137,7 +138,7 @@ u32 gk20a_pmu_get_irqdest(struct gk20a *g) | |||
137 | return intr_dest; | 138 | return intr_dest; |
138 | } | 139 | } |
139 | 140 | ||
140 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) | 141 | void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable) |
141 | { | 142 | { |
142 | struct gk20a *g = gk20a_from_pmu(pmu); | 143 | struct gk20a *g = gk20a_from_pmu(pmu); |
143 | u32 intr_mask; | 144 | u32 intr_mask; |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index d9c53c28..ee7ee8c7 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -67,9 +67,7 @@ int pmu_bootstrap(struct nvgpu_pmu *pmu); | |||
67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); | 67 | void gk20a_pmu_dump_elpg_stats(struct nvgpu_pmu *pmu); |
68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); | 68 | void gk20a_pmu_dump_falcon_stats(struct nvgpu_pmu *pmu); |
69 | 69 | ||
70 | void pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); | 70 | void gk20a_pmu_enable_irq(struct nvgpu_pmu *pmu, bool enable); |
71 | int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | ||
72 | void *var, u8 val); | ||
73 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | 71 | void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, |
74 | void *param, u32 handle, u32 status); | 72 | void *param, u32 handle, u32 status); |
75 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, | 73 | void gk20a_pmu_elpg_statistics(struct gk20a *g, u32 pg_engine_id, |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 916e7a66..9725ebe7 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -37,16 +37,11 @@ | |||
37 | #include <nvgpu/utils.h> | 37 | #include <nvgpu/utils.h> |
38 | 38 | ||
39 | #include "gk20a/gk20a.h" | 39 | #include "gk20a/gk20a.h" |
40 | #include "gk20a/pmu_gk20a.h" | ||
41 | #include "mm_gm20b.h" | 40 | #include "mm_gm20b.h" |
42 | #include "acr_gm20b.h" | 41 | #include "acr_gm20b.h" |
43 | 42 | ||
44 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 43 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
45 | 44 | ||
46 | /*Defines*/ | ||
47 | #define gm20b_dbg_pmu(g, fmt, arg...) \ | ||
48 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | ||
49 | |||
50 | typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata); | 45 | typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata); |
51 | 46 | ||
52 | /*Externs*/ | 47 | /*Externs*/ |
@@ -80,7 +75,7 @@ static void start_gm20b_pmu(struct gk20a *g) | |||
80 | { | 75 | { |
81 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 76 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
82 | nvgpu_mutex_acquire(&g->pmu.isr_mutex); | 77 | nvgpu_mutex_acquire(&g->pmu.isr_mutex); |
83 | pmu_enable_irq(&g->pmu, true); | 78 | g->ops.pmu.pmu_enable_irq(&g->pmu, true); |
84 | g->pmu.isr_enabled = true; | 79 | g->pmu.isr_enabled = true; |
85 | nvgpu_mutex_release(&g->pmu.isr_mutex); | 80 | nvgpu_mutex_release(&g->pmu.isr_mutex); |
86 | gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), | 81 | gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), |
@@ -103,16 +98,16 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
103 | struct nvgpu_pmu *pmu = &g->pmu; | 98 | struct nvgpu_pmu *pmu = &g->pmu; |
104 | struct lsf_ucode_desc *lsf_desc; | 99 | struct lsf_ucode_desc *lsf_desc; |
105 | int err; | 100 | int err; |
106 | gm20b_dbg_pmu(g, "requesting PMU ucode in GM20B\n"); | 101 | nvgpu_pmu_dbg(g, "requesting PMU ucode in GM20B\n"); |
107 | pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE, 0); | 102 | pmu_fw = nvgpu_request_firmware(g, GM20B_PMU_UCODE_IMAGE, 0); |
108 | if (!pmu_fw) { | 103 | if (!pmu_fw) { |
109 | nvgpu_err(g, "failed to load pmu ucode!!"); | 104 | nvgpu_err(g, "failed to load pmu ucode!!"); |
110 | return -ENOENT; | 105 | return -ENOENT; |
111 | } | 106 | } |
112 | g->acr.pmu_fw = pmu_fw; | 107 | g->acr.pmu_fw = pmu_fw; |
113 | gm20b_dbg_pmu(g, "Loaded PMU ucode in for blob preparation"); | 108 | nvgpu_pmu_dbg(g, "Loaded PMU ucode in for blob preparation"); |
114 | 109 | ||
115 | gm20b_dbg_pmu(g, "requesting PMU ucode desc in GM20B\n"); | 110 | nvgpu_pmu_dbg(g, "requesting PMU ucode desc in GM20B\n"); |
116 | pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC, 0); | 111 | pmu_desc = nvgpu_request_firmware(g, GM20B_PMU_UCODE_DESC, 0); |
117 | if (!pmu_desc) { | 112 | if (!pmu_desc) { |
118 | nvgpu_err(g, "failed to load pmu ucode desc!!"); | 113 | nvgpu_err(g, "failed to load pmu ucode desc!!"); |
@@ -131,7 +126,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
131 | 126 | ||
132 | err = nvgpu_init_pmu_fw_support(pmu); | 127 | err = nvgpu_init_pmu_fw_support(pmu); |
133 | if (err) { | 128 | if (err) { |
134 | gm20b_dbg_pmu(g, "failed to set function pointers\n"); | 129 | nvgpu_pmu_dbg(g, "failed to set function pointers\n"); |
135 | goto release_sig; | 130 | goto release_sig; |
136 | } | 131 | } |
137 | 132 | ||
@@ -150,7 +145,7 @@ static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
150 | p_img->fw_ver = NULL; | 145 | p_img->fw_ver = NULL; |
151 | p_img->header = NULL; | 146 | p_img->header = NULL; |
152 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; | 147 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; |
153 | gm20b_dbg_pmu(g, "requesting PMU ucode in GM20B exit\n"); | 148 | nvgpu_pmu_dbg(g, "requesting PMU ucode in GM20B exit\n"); |
154 | nvgpu_release_firmware(g, pmu_sig); | 149 | nvgpu_release_firmware(g, pmu_sig); |
155 | return 0; | 150 | return 0; |
156 | release_sig: | 151 | release_sig: |
@@ -223,7 +218,7 @@ static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
223 | p_img->fw_ver = NULL; | 218 | p_img->fw_ver = NULL; |
224 | p_img->header = NULL; | 219 | p_img->header = NULL; |
225 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; | 220 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; |
226 | gm20b_dbg_pmu(g, "fecs fw loaded\n"); | 221 | nvgpu_pmu_dbg(g, "fecs fw loaded\n"); |
227 | nvgpu_release_firmware(g, fecs_sig); | 222 | nvgpu_release_firmware(g, fecs_sig); |
228 | return 0; | 223 | return 0; |
229 | free_lsf_desc: | 224 | free_lsf_desc: |
@@ -295,7 +290,7 @@ static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img) | |||
295 | p_img->fw_ver = NULL; | 290 | p_img->fw_ver = NULL; |
296 | p_img->header = NULL; | 291 | p_img->header = NULL; |
297 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; | 292 | p_img->lsf_desc = (struct lsf_ucode_desc *)lsf_desc; |
298 | gm20b_dbg_pmu(g, "gpccs fw loaded\n"); | 293 | nvgpu_pmu_dbg(g, "gpccs fw loaded\n"); |
299 | nvgpu_release_firmware(g, gpccs_sig); | 294 | nvgpu_release_firmware(g, gpccs_sig); |
300 | return 0; | 295 | return 0; |
301 | free_lsf_desc: | 296 | free_lsf_desc: |
@@ -364,24 +359,24 @@ int prepare_ucode_blob(struct gk20a *g) | |||
364 | non WPR blob of ucodes*/ | 359 | non WPR blob of ucodes*/ |
365 | err = nvgpu_init_pmu_fw_support(pmu); | 360 | err = nvgpu_init_pmu_fw_support(pmu); |
366 | if (err) { | 361 | if (err) { |
367 | gm20b_dbg_pmu(g, "failed to set function pointers\n"); | 362 | nvgpu_pmu_dbg(g, "failed to set function pointers\n"); |
368 | return err; | 363 | return err; |
369 | } | 364 | } |
370 | return 0; | 365 | return 0; |
371 | } | 366 | } |
372 | plsfm = &lsfm_l; | 367 | plsfm = &lsfm_l; |
373 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr)); | 368 | memset((void *)plsfm, 0, sizeof(struct ls_flcn_mgr)); |
374 | gm20b_dbg_pmu(g, "fetching GMMU regs\n"); | 369 | nvgpu_pmu_dbg(g, "fetching GMMU regs\n"); |
375 | g->ops.fb.vpr_info_fetch(g); | 370 | g->ops.fb.vpr_info_fetch(g); |
376 | gr_gk20a_init_ctxsw_ucode(g); | 371 | gr_gk20a_init_ctxsw_ucode(g); |
377 | 372 | ||
378 | g->ops.pmu.get_wpr(g, &wpr_inf); | 373 | g->ops.pmu.get_wpr(g, &wpr_inf); |
379 | gm20b_dbg_pmu(g, "wpr carveout base:%llx\n", wpr_inf.wpr_base); | 374 | nvgpu_pmu_dbg(g, "wpr carveout base:%llx\n", wpr_inf.wpr_base); |
380 | gm20b_dbg_pmu(g, "wpr carveout size :%llx\n", wpr_inf.size); | 375 | nvgpu_pmu_dbg(g, "wpr carveout size :%llx\n", wpr_inf.size); |
381 | 376 | ||
382 | /* Discover all managed falcons*/ | 377 | /* Discover all managed falcons*/ |
383 | err = lsfm_discover_ucode_images(g, plsfm); | 378 | err = lsfm_discover_ucode_images(g, plsfm); |
384 | gm20b_dbg_pmu(g, " Managed Falcon cnt %d\n", plsfm->managed_flcn_cnt); | 379 | nvgpu_pmu_dbg(g, " Managed Falcon cnt %d\n", plsfm->managed_flcn_cnt); |
385 | if (err) { | 380 | if (err) { |
386 | goto free_sgt; | 381 | goto free_sgt; |
387 | } | 382 | } |
@@ -400,13 +395,13 @@ int prepare_ucode_blob(struct gk20a *g) | |||
400 | goto free_sgt; | 395 | goto free_sgt; |
401 | } | 396 | } |
402 | 397 | ||
403 | gm20b_dbg_pmu(g, "managed LS falcon %d, WPR size %d bytes.\n", | 398 | nvgpu_pmu_dbg(g, "managed LS falcon %d, WPR size %d bytes.\n", |
404 | plsfm->managed_flcn_cnt, plsfm->wpr_size); | 399 | plsfm->managed_flcn_cnt, plsfm->wpr_size); |
405 | lsfm_init_wpr_contents(g, plsfm, &g->acr.ucode_blob); | 400 | lsfm_init_wpr_contents(g, plsfm, &g->acr.ucode_blob); |
406 | } else { | 401 | } else { |
407 | gm20b_dbg_pmu(g, "LSFM is managing no falcons.\n"); | 402 | nvgpu_pmu_dbg(g, "LSFM is managing no falcons.\n"); |
408 | } | 403 | } |
409 | gm20b_dbg_pmu(g, "prepare ucode blob return 0\n"); | 404 | nvgpu_pmu_dbg(g, "prepare ucode blob return 0\n"); |
410 | free_acr_resources(g, plsfm); | 405 | free_acr_resources(g, plsfm); |
411 | free_sgt: | 406 | free_sgt: |
412 | return err; | 407 | return err; |
@@ -452,13 +447,13 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
452 | 447 | ||
453 | plsfm->managed_flcn_cnt++; | 448 | plsfm->managed_flcn_cnt++; |
454 | } else { | 449 | } else { |
455 | gm20b_dbg_pmu(g, "id not managed %d\n", | 450 | nvgpu_pmu_dbg(g, "id not managed %d\n", |
456 | ucode_img.lsf_desc->falcon_id); | 451 | ucode_img.lsf_desc->falcon_id); |
457 | } | 452 | } |
458 | 453 | ||
459 | /*Free any ucode image resources if not managing this falcon*/ | 454 | /*Free any ucode image resources if not managing this falcon*/ |
460 | if (!(pmu->pmu_mode & PMU_LSFM_MANAGED)) { | 455 | if (!(pmu->pmu_mode & PMU_LSFM_MANAGED)) { |
461 | gm20b_dbg_pmu(g, "pmu is not LSFM managed\n"); | 456 | nvgpu_pmu_dbg(g, "pmu is not LSFM managed\n"); |
462 | lsfm_free_ucode_img_res(g, &ucode_img); | 457 | lsfm_free_ucode_img_res(g, &ucode_img); |
463 | } | 458 | } |
464 | 459 | ||
@@ -490,7 +485,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
490 | plsfm->managed_flcn_cnt++; | 485 | plsfm->managed_flcn_cnt++; |
491 | } | 486 | } |
492 | } else { | 487 | } else { |
493 | gm20b_dbg_pmu(g, "not managed %d\n", | 488 | nvgpu_pmu_dbg(g, "not managed %d\n", |
494 | ucode_img.lsf_desc->falcon_id); | 489 | ucode_img.lsf_desc->falcon_id); |
495 | lsfm_free_nonpmu_ucode_img_res(g, | 490 | lsfm_free_nonpmu_ucode_img_res(g, |
496 | &ucode_img); | 491 | &ucode_img); |
@@ -498,7 +493,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g, | |||
498 | } | 493 | } |
499 | } else { | 494 | } else { |
500 | /* Consumed all available falcon objects */ | 495 | /* Consumed all available falcon objects */ |
501 | gm20b_dbg_pmu(g, "Done checking for ucodes %d\n", i); | 496 | nvgpu_pmu_dbg(g, "Done checking for ucodes %d\n", i); |
502 | break; | 497 | break; |
503 | } | 498 | } |
504 | } | 499 | } |
@@ -539,26 +534,26 @@ int gm20b_pmu_populate_loader_cfg(struct gk20a *g, | |||
539 | addr_base = p_lsfm->lsb_header.ucode_off; | 534 | addr_base = p_lsfm->lsb_header.ucode_off; |
540 | g->ops.pmu.get_wpr(g, &wpr_inf); | 535 | g->ops.pmu.get_wpr(g, &wpr_inf); |
541 | addr_base += wpr_inf.wpr_base; | 536 | addr_base += wpr_inf.wpr_base; |
542 | gm20b_dbg_pmu(g, "pmu loader cfg u32 addrbase %x\n", (u32)addr_base); | 537 | nvgpu_pmu_dbg(g, "pmu loader cfg u32 addrbase %x\n", (u32)addr_base); |
543 | /*From linux*/ | 538 | /*From linux*/ |
544 | addr_code = u64_lo32((addr_base + | 539 | addr_code = u64_lo32((addr_base + |
545 | desc->app_start_offset + | 540 | desc->app_start_offset + |
546 | desc->app_resident_code_offset) >> 8); | 541 | desc->app_resident_code_offset) >> 8); |
547 | gm20b_dbg_pmu(g, "app start %d app res code off %d\n", | 542 | nvgpu_pmu_dbg(g, "app start %d app res code off %d\n", |
548 | desc->app_start_offset, desc->app_resident_code_offset); | 543 | desc->app_start_offset, desc->app_resident_code_offset); |
549 | addr_data = u64_lo32((addr_base + | 544 | addr_data = u64_lo32((addr_base + |
550 | desc->app_start_offset + | 545 | desc->app_start_offset + |
551 | desc->app_resident_data_offset) >> 8); | 546 | desc->app_resident_data_offset) >> 8); |
552 | gm20b_dbg_pmu(g, "app res data offset%d\n", | 547 | nvgpu_pmu_dbg(g, "app res data offset%d\n", |
553 | desc->app_resident_data_offset); | 548 | desc->app_resident_data_offset); |
554 | gm20b_dbg_pmu(g, "bl start off %d\n", desc->bootloader_start_offset); | 549 | nvgpu_pmu_dbg(g, "bl start off %d\n", desc->bootloader_start_offset); |
555 | 550 | ||
556 | addr_args = ((pwr_falcon_hwcfg_dmem_size_v( | 551 | addr_args = ((pwr_falcon_hwcfg_dmem_size_v( |
557 | gk20a_readl(g, pwr_falcon_hwcfg_r()))) | 552 | gk20a_readl(g, pwr_falcon_hwcfg_r()))) |
558 | << GK20A_PMU_DMEM_BLKSIZE2); | 553 | << GK20A_PMU_DMEM_BLKSIZE2); |
559 | addr_args -= g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); | 554 | addr_args -= g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu); |
560 | 555 | ||
561 | gm20b_dbg_pmu(g, "addr_args %x\n", addr_args); | 556 | nvgpu_pmu_dbg(g, "addr_args %x\n", addr_args); |
562 | 557 | ||
563 | /* Populate the loader_config state*/ | 558 | /* Populate the loader_config state*/ |
564 | ldr_cfg->dma_idx = GK20A_PMU_DMAIDX_UCODE; | 559 | ldr_cfg->dma_idx = GK20A_PMU_DMAIDX_UCODE; |
@@ -616,7 +611,7 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
616 | g->ops.pmu.get_wpr(g, &wpr_inf); | 611 | g->ops.pmu.get_wpr(g, &wpr_inf); |
617 | addr_base += wpr_inf.wpr_base; | 612 | addr_base += wpr_inf.wpr_base; |
618 | 613 | ||
619 | gm20b_dbg_pmu(g, "gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, | 614 | nvgpu_pmu_dbg(g, "gen loader cfg %x u32 addrbase %x ID\n", (u32)addr_base, |
620 | p_lsfm->wpr_header.falcon_id); | 615 | p_lsfm->wpr_header.falcon_id); |
621 | addr_code = u64_lo32((addr_base + | 616 | addr_code = u64_lo32((addr_base + |
622 | desc->app_start_offset + | 617 | desc->app_start_offset + |
@@ -625,7 +620,7 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
625 | desc->app_start_offset + | 620 | desc->app_start_offset + |
626 | desc->app_resident_data_offset) >> 8); | 621 | desc->app_resident_data_offset) >> 8); |
627 | 622 | ||
628 | gm20b_dbg_pmu(g, "gen cfg %x u32 addrcode %x & data %x load offset %xID\n", | 623 | nvgpu_pmu_dbg(g, "gen cfg %x u32 addrcode %x & data %x load offset %xID\n", |
629 | (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset, | 624 | (u32)addr_code, (u32)addr_data, desc->bootloader_start_offset, |
630 | p_lsfm->wpr_header.falcon_id); | 625 | p_lsfm->wpr_header.falcon_id); |
631 | 626 | ||
@@ -648,7 +643,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
648 | 643 | ||
649 | struct nvgpu_pmu *pmu = &g->pmu; | 644 | struct nvgpu_pmu *pmu = &g->pmu; |
650 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { | 645 | if (pnode->wpr_header.falcon_id != pmu->falcon_id) { |
651 | gm20b_dbg_pmu(g, "non pmu. write flcn bl gen desc\n"); | 646 | nvgpu_pmu_dbg(g, "non pmu. write flcn bl gen desc\n"); |
652 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, | 647 | g->ops.pmu.flcn_populate_bl_dmem_desc(g, |
653 | pnode, &pnode->bl_gen_desc_size, | 648 | pnode, &pnode->bl_gen_desc_size, |
654 | pnode->wpr_header.falcon_id); | 649 | pnode->wpr_header.falcon_id); |
@@ -656,7 +651,7 @@ static int lsfm_fill_flcn_bl_gen_desc(struct gk20a *g, | |||
656 | } | 651 | } |
657 | 652 | ||
658 | if (pmu->pmu_mode & PMU_LSFM_MANAGED) { | 653 | if (pmu->pmu_mode & PMU_LSFM_MANAGED) { |
659 | gm20b_dbg_pmu(g, "pmu write flcn bl gen desc\n"); | 654 | nvgpu_pmu_dbg(g, "pmu write flcn bl gen desc\n"); |
660 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) { | 655 | if (pnode->wpr_header.falcon_id == pmu->falcon_id) { |
661 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, | 656 | return g->ops.pmu.pmu_populate_loader_cfg(g, pnode, |
662 | &pnode->bl_gen_desc_size); | 657 | &pnode->bl_gen_desc_size); |
@@ -690,46 +685,46 @@ static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm, | |||
690 | nvgpu_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), | 685 | nvgpu_mem_wr_n(g, ucode, i * sizeof(pnode->wpr_header), |
691 | &pnode->wpr_header, sizeof(pnode->wpr_header)); | 686 | &pnode->wpr_header, sizeof(pnode->wpr_header)); |
692 | 687 | ||
693 | gm20b_dbg_pmu(g, "wpr header"); | 688 | nvgpu_pmu_dbg(g, "wpr header"); |
694 | gm20b_dbg_pmu(g, "falconid :%d", | 689 | nvgpu_pmu_dbg(g, "falconid :%d", |
695 | pnode->wpr_header.falcon_id); | 690 | pnode->wpr_header.falcon_id); |
696 | gm20b_dbg_pmu(g, "lsb_offset :%x", | 691 | nvgpu_pmu_dbg(g, "lsb_offset :%x", |
697 | pnode->wpr_header.lsb_offset); | 692 | pnode->wpr_header.lsb_offset); |
698 | gm20b_dbg_pmu(g, "bootstrap_owner :%d", | 693 | nvgpu_pmu_dbg(g, "bootstrap_owner :%d", |
699 | pnode->wpr_header.bootstrap_owner); | 694 | pnode->wpr_header.bootstrap_owner); |
700 | gm20b_dbg_pmu(g, "lazy_bootstrap :%d", | 695 | nvgpu_pmu_dbg(g, "lazy_bootstrap :%d", |
701 | pnode->wpr_header.lazy_bootstrap); | 696 | pnode->wpr_header.lazy_bootstrap); |
702 | gm20b_dbg_pmu(g, "status :%d", | 697 | nvgpu_pmu_dbg(g, "status :%d", |
703 | pnode->wpr_header.status); | 698 | pnode->wpr_header.status); |
704 | 699 | ||
705 | /*Flush LSB header to memory*/ | 700 | /*Flush LSB header to memory*/ |
706 | nvgpu_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, | 701 | nvgpu_mem_wr_n(g, ucode, pnode->wpr_header.lsb_offset, |
707 | &pnode->lsb_header, sizeof(pnode->lsb_header)); | 702 | &pnode->lsb_header, sizeof(pnode->lsb_header)); |
708 | 703 | ||
709 | gm20b_dbg_pmu(g, "lsb header"); | 704 | nvgpu_pmu_dbg(g, "lsb header"); |
710 | gm20b_dbg_pmu(g, "ucode_off :%x", | 705 | nvgpu_pmu_dbg(g, "ucode_off :%x", |
711 | pnode->lsb_header.ucode_off); | 706 | pnode->lsb_header.ucode_off); |
712 | gm20b_dbg_pmu(g, "ucode_size :%x", | 707 | nvgpu_pmu_dbg(g, "ucode_size :%x", |
713 | pnode->lsb_header.ucode_size); | 708 | pnode->lsb_header.ucode_size); |
714 | gm20b_dbg_pmu(g, "data_size :%x", | 709 | nvgpu_pmu_dbg(g, "data_size :%x", |
715 | pnode->lsb_header.data_size); | 710 | pnode->lsb_header.data_size); |
716 | gm20b_dbg_pmu(g, "bl_code_size :%x", | 711 | nvgpu_pmu_dbg(g, "bl_code_size :%x", |
717 | pnode->lsb_header.bl_code_size); | 712 | pnode->lsb_header.bl_code_size); |
718 | gm20b_dbg_pmu(g, "bl_imem_off :%x", | 713 | nvgpu_pmu_dbg(g, "bl_imem_off :%x", |
719 | pnode->lsb_header.bl_imem_off); | 714 | pnode->lsb_header.bl_imem_off); |
720 | gm20b_dbg_pmu(g, "bl_data_off :%x", | 715 | nvgpu_pmu_dbg(g, "bl_data_off :%x", |
721 | pnode->lsb_header.bl_data_off); | 716 | pnode->lsb_header.bl_data_off); |
722 | gm20b_dbg_pmu(g, "bl_data_size :%x", | 717 | nvgpu_pmu_dbg(g, "bl_data_size :%x", |
723 | pnode->lsb_header.bl_data_size); | 718 | pnode->lsb_header.bl_data_size); |
724 | gm20b_dbg_pmu(g, "app_code_off :%x", | 719 | nvgpu_pmu_dbg(g, "app_code_off :%x", |
725 | pnode->lsb_header.app_code_off); | 720 | pnode->lsb_header.app_code_off); |
726 | gm20b_dbg_pmu(g, "app_code_size :%x", | 721 | nvgpu_pmu_dbg(g, "app_code_size :%x", |
727 | pnode->lsb_header.app_code_size); | 722 | pnode->lsb_header.app_code_size); |
728 | gm20b_dbg_pmu(g, "app_data_off :%x", | 723 | nvgpu_pmu_dbg(g, "app_data_off :%x", |
729 | pnode->lsb_header.app_data_off); | 724 | pnode->lsb_header.app_data_off); |
730 | gm20b_dbg_pmu(g, "app_data_size :%x", | 725 | nvgpu_pmu_dbg(g, "app_data_size :%x", |
731 | pnode->lsb_header.app_data_size); | 726 | pnode->lsb_header.app_data_size); |
732 | gm20b_dbg_pmu(g, "flags :%x", | 727 | nvgpu_pmu_dbg(g, "flags :%x", |
733 | pnode->lsb_header.flags); | 728 | pnode->lsb_header.flags); |
734 | 729 | ||
735 | /*If this falcon has a boot loader and related args, | 730 | /*If this falcon has a boot loader and related args, |
@@ -1049,7 +1044,7 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1049 | start = nvgpu_mem_get_addr(g, &acr->ucode_blob); | 1044 | start = nvgpu_mem_get_addr(g, &acr->ucode_blob); |
1050 | size = acr->ucode_blob.size; | 1045 | size = acr->ucode_blob.size; |
1051 | 1046 | ||
1052 | gm20b_dbg_pmu(g, " "); | 1047 | nvgpu_pmu_dbg(g, " "); |
1053 | 1048 | ||
1054 | if (!acr_fw) { | 1049 | if (!acr_fw) { |
1055 | /*First time init case*/ | 1050 | /*First time init case*/ |
@@ -1163,14 +1158,14 @@ int acr_ucode_patch_sig(struct gk20a *g, | |||
1163 | unsigned int *p_patch_ind) | 1158 | unsigned int *p_patch_ind) |
1164 | { | 1159 | { |
1165 | unsigned int i, *p_sig; | 1160 | unsigned int i, *p_sig; |
1166 | gm20b_dbg_pmu(g, " "); | 1161 | nvgpu_pmu_dbg(g, " "); |
1167 | 1162 | ||
1168 | if (!pmu_is_debug_mode_en(g)) { | 1163 | if (!pmu_is_debug_mode_en(g)) { |
1169 | p_sig = p_prod_sig; | 1164 | p_sig = p_prod_sig; |
1170 | gm20b_dbg_pmu(g, "PRODUCTION MODE\n"); | 1165 | nvgpu_pmu_dbg(g, "PRODUCTION MODE\n"); |
1171 | } else { | 1166 | } else { |
1172 | p_sig = p_dbg_sig; | 1167 | p_sig = p_dbg_sig; |
1173 | gm20b_dbg_pmu(g, "DEBUG MODE\n"); | 1168 | nvgpu_pmu_dbg(g, "DEBUG MODE\n"); |
1174 | } | 1169 | } |
1175 | 1170 | ||
1176 | /* Patching logic:*/ | 1171 | /* Patching logic:*/ |
@@ -1303,7 +1298,7 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1303 | 1298 | ||
1304 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 1299 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
1305 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 1300 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
1306 | pmu_enable_irq(pmu, false); | 1301 | g->ops.pmu.pmu_enable_irq(pmu, false); |
1307 | pmu->isr_enabled = false; | 1302 | pmu->isr_enabled = false; |
1308 | nvgpu_mutex_release(&pmu->isr_mutex); | 1303 | nvgpu_mutex_release(&pmu->isr_mutex); |
1309 | /*Clearing mailbox register used to reflect capabilities*/ | 1304 | /*Clearing mailbox register used to reflect capabilities*/ |
@@ -1335,7 +1330,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1335 | struct nvgpu_firmware *hsbl_fw = acr->hsbl_fw; | 1330 | struct nvgpu_firmware *hsbl_fw = acr->hsbl_fw; |
1336 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc; | 1331 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc; |
1337 | u32 *pmu_bl_gm10x = NULL; | 1332 | u32 *pmu_bl_gm10x = NULL; |
1338 | gm20b_dbg_pmu(g, " "); | 1333 | nvgpu_pmu_dbg(g, " "); |
1339 | 1334 | ||
1340 | if (!hsbl_fw) { | 1335 | if (!hsbl_fw) { |
1341 | hsbl_fw = nvgpu_request_firmware(g, | 1336 | hsbl_fw = nvgpu_request_firmware(g, |
@@ -1354,7 +1349,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1354 | bl_sz = ALIGN(pmu_bl_gm10x_desc->bl_img_hdr.bl_code_size, | 1349 | bl_sz = ALIGN(pmu_bl_gm10x_desc->bl_img_hdr.bl_code_size, |
1355 | 256); | 1350 | 256); |
1356 | acr->hsbl_ucode.size = bl_sz; | 1351 | acr->hsbl_ucode.size = bl_sz; |
1357 | gm20b_dbg_pmu(g, "Executing Generic Bootloader\n"); | 1352 | nvgpu_pmu_dbg(g, "Executing Generic Bootloader\n"); |
1358 | 1353 | ||
1359 | /*TODO in code verify that enable PMU is done, | 1354 | /*TODO in code verify that enable PMU is done, |
1360 | scrubbing etc is done*/ | 1355 | scrubbing etc is done*/ |
@@ -1377,7 +1372,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1377 | } | 1372 | } |
1378 | 1373 | ||
1379 | nvgpu_mem_wr_n(g, &acr->hsbl_ucode, 0, pmu_bl_gm10x, bl_sz); | 1374 | nvgpu_mem_wr_n(g, &acr->hsbl_ucode, 0, pmu_bl_gm10x, bl_sz); |
1380 | gm20b_dbg_pmu(g, "Copied bl ucode to bl_cpuva\n"); | 1375 | nvgpu_pmu_dbg(g, "Copied bl ucode to bl_cpuva\n"); |
1381 | } | 1376 | } |
1382 | /* | 1377 | /* |
1383 | * Disable interrupts to avoid kernel hitting breakpoint due | 1378 | * Disable interrupts to avoid kernel hitting breakpoint due |
@@ -1389,9 +1384,9 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1389 | goto err_unmap_bl; | 1384 | goto err_unmap_bl; |
1390 | } | 1385 | } |
1391 | 1386 | ||
1392 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, | 1387 | nvgpu_pmu_dbg(g, "phys sec reg %x\n", gk20a_readl(g, |
1393 | pwr_falcon_mmu_phys_sec_r())); | 1388 | pwr_falcon_mmu_phys_sec_r())); |
1394 | gm20b_dbg_pmu(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); | 1389 | nvgpu_pmu_dbg(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); |
1395 | 1390 | ||
1396 | g->ops.pmu.init_falcon_setup_hw(g, desc, acr->hsbl_ucode.size); | 1391 | g->ops.pmu.init_falcon_setup_hw(g, desc, acr->hsbl_ucode.size); |
1397 | 1392 | ||
@@ -1409,10 +1404,10 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1409 | goto err_unmap_bl; | 1404 | goto err_unmap_bl; |
1410 | } | 1405 | } |
1411 | } | 1406 | } |
1412 | gm20b_dbg_pmu(g, "after waiting for halt, err %x\n", err); | 1407 | nvgpu_pmu_dbg(g, "after waiting for halt, err %x\n", err); |
1413 | gm20b_dbg_pmu(g, "phys sec reg %x\n", gk20a_readl(g, | 1408 | nvgpu_pmu_dbg(g, "phys sec reg %x\n", gk20a_readl(g, |
1414 | pwr_falcon_mmu_phys_sec_r())); | 1409 | pwr_falcon_mmu_phys_sec_r())); |
1415 | gm20b_dbg_pmu(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); | 1410 | nvgpu_pmu_dbg(g, "sctl reg %x\n", gk20a_readl(g, pwr_falcon_sctl_r())); |
1416 | start_gm20b_pmu(g); | 1411 | start_gm20b_pmu(g); |
1417 | return 0; | 1412 | return 0; |
1418 | err_unmap_bl: | 1413 | err_unmap_bl: |
@@ -1443,7 +1438,7 @@ int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms) | |||
1443 | } | 1438 | } |
1444 | 1439 | ||
1445 | g->acr.capabilities = gk20a_readl(g, pwr_falcon_mailbox1_r()); | 1440 | g->acr.capabilities = gk20a_readl(g, pwr_falcon_mailbox1_r()); |
1446 | gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); | 1441 | nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities); |
1447 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); | 1442 | data = gk20a_readl(g, pwr_falcon_mailbox0_r()); |
1448 | if (data) { | 1443 | if (data) { |
1449 | nvgpu_err(g, "ACR boot failed, err %x", data); | 1444 | nvgpu_err(g, "ACR boot failed, err %x", data); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 27daccb6..835d18d4 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -525,6 +525,15 @@ static const struct gpu_ops gm20b_ops = { | |||
525 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 525 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, |
526 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | 526 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, |
527 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 527 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
528 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | ||
529 | .pmu_isr = gk20a_pmu_isr, | ||
530 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | ||
531 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | ||
532 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | ||
533 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | ||
534 | .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, | ||
535 | .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, | ||
536 | .pmu_enable_irq = gk20a_pmu_enable_irq, | ||
528 | .write_dmatrfbase = gm20b_write_dmatrfbase, | 537 | .write_dmatrfbase = gm20b_write_dmatrfbase, |
529 | .pmu_elpg_statistics = gk20a_pmu_elpg_statistics, | 538 | .pmu_elpg_statistics = gk20a_pmu_elpg_statistics, |
530 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, | 539 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 286a1979..38970f73 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -37,10 +37,6 @@ | |||
37 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | 37 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> |
38 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 38 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
39 | 39 | ||
40 | #define gm20b_dbg_pmu(g, fmt, arg...) \ | ||
41 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | ||
42 | |||
43 | |||
44 | /* PROD settings for ELPG sequencing registers*/ | 40 | /* PROD settings for ELPG sequencing registers*/ |
45 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { | 41 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { |
46 | { 0x0010ab10, 0x8180}, | 42 | { 0x0010ab10, 0x8180}, |
@@ -129,7 +125,7 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
129 | { | 125 | { |
130 | nvgpu_log_fn(g, " "); | 126 | nvgpu_log_fn(g, " "); |
131 | 127 | ||
132 | gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); | 128 | nvgpu_pmu_dbg(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); |
133 | 129 | ||
134 | if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) { | 130 | if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) { |
135 | g->pmu_lsf_pmu_wpr_init_done = 1; | 131 | g->pmu_lsf_pmu_wpr_init_done = 1; |
@@ -154,7 +150,7 @@ int gm20b_pmu_init_acr(struct gk20a *g) | |||
154 | cmd.cmd.acr.init_wpr.cmd_type = PMU_ACR_CMD_ID_INIT_WPR_REGION; | 150 | cmd.cmd.acr.init_wpr.cmd_type = PMU_ACR_CMD_ID_INIT_WPR_REGION; |
155 | cmd.cmd.acr.init_wpr.regionid = 0x01; | 151 | cmd.cmd.acr.init_wpr.regionid = 0x01; |
156 | cmd.cmd.acr.init_wpr.wproffset = 0x00; | 152 | cmd.cmd.acr.init_wpr.wproffset = 0x00; |
157 | gm20b_dbg_pmu(g, "cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); | 153 | nvgpu_pmu_dbg(g, "cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); |
158 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 154 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
159 | pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); | 155 | pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); |
160 | 156 | ||
@@ -169,9 +165,9 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
169 | nvgpu_log_fn(g, " "); | 165 | nvgpu_log_fn(g, " "); |
170 | 166 | ||
171 | 167 | ||
172 | gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON"); | 168 | nvgpu_pmu_dbg(g, "reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON"); |
173 | 169 | ||
174 | gm20b_dbg_pmu(g, "response code = %x\n", msg->msg.acr.acrmsg.falconid); | 170 | nvgpu_pmu_dbg(g, "response code = %x\n", msg->msg.acr.acrmsg.falconid); |
175 | g->pmu_lsf_loaded_falcon_id = msg->msg.acr.acrmsg.falconid; | 171 | g->pmu_lsf_loaded_falcon_id = msg->msg.acr.acrmsg.falconid; |
176 | nvgpu_log_fn(g, "done"); | 172 | nvgpu_log_fn(g, "done"); |
177 | } | 173 | } |
@@ -207,7 +203,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags) | |||
207 | 203 | ||
208 | nvgpu_log_fn(g, " "); | 204 | nvgpu_log_fn(g, " "); |
209 | 205 | ||
210 | gm20b_dbg_pmu(g, "wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done); | 206 | nvgpu_pmu_dbg(g, "wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done); |
211 | if (g->pmu_lsf_pmu_wpr_init_done) { | 207 | if (g->pmu_lsf_pmu_wpr_init_done) { |
212 | /* send message to load FECS falcon */ | 208 | /* send message to load FECS falcon */ |
213 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 209 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
@@ -218,7 +214,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags) | |||
218 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON; | 214 | PMU_ACR_CMD_ID_BOOTSTRAP_FALCON; |
219 | cmd.cmd.acr.bootstrap_falcon.flags = flags; | 215 | cmd.cmd.acr.bootstrap_falcon.flags = flags; |
220 | cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; | 216 | cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; |
221 | gm20b_dbg_pmu(g, "cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n", | 217 | nvgpu_pmu_dbg(g, "cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n", |
222 | falcon_id); | 218 | falcon_id); |
223 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | 219 | nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, |
224 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); | 220 | pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); |
diff --git a/drivers/gpu/nvgpu/gp106/acr_gp106.c b/drivers/gpu/nvgpu/gp106/acr_gp106.c index 795ae0d8..9b8558db 100644 --- a/drivers/gpu/nvgpu/gp106/acr_gp106.c +++ b/drivers/gpu/nvgpu/gp106/acr_gp106.c | |||
@@ -31,7 +31,6 @@ | |||
31 | #include <nvgpu/utils.h> | 31 | #include <nvgpu/utils.h> |
32 | 32 | ||
33 | #include "gk20a/gk20a.h" | 33 | #include "gk20a/gk20a.h" |
34 | #include "gk20a/pmu_gk20a.h" | ||
35 | 34 | ||
36 | #include "gm20b/mm_gm20b.h" | 35 | #include "gm20b/mm_gm20b.h" |
37 | #include "gm20b/acr_gm20b.h" | 36 | #include "gm20b/acr_gm20b.h" |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 9c42ac3a..54648f56 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -634,6 +634,15 @@ static const struct gpu_ops gp106_ops = { | |||
634 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 634 | .pmu_queue_tail = gk20a_pmu_queue_tail, |
635 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 635 | .pmu_get_queue_head = pwr_pmu_queue_head_r, |
636 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 636 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
637 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | ||
638 | .pmu_isr = gk20a_pmu_isr, | ||
639 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | ||
640 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | ||
641 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | ||
642 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | ||
643 | .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, | ||
644 | .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, | ||
645 | .pmu_enable_irq = gk20a_pmu_enable_irq, | ||
637 | .is_pmu_supported = gp106_is_pmu_supported, | 646 | .is_pmu_supported = gp106_is_pmu_supported, |
638 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | 647 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, |
639 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | 648 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, |
diff --git a/drivers/gpu/nvgpu/gp106/sec2_gp106.c b/drivers/gpu/nvgpu/gp106/sec2_gp106.c index 61424bfe..dec35a91 100644 --- a/drivers/gpu/nvgpu/gp106/sec2_gp106.c +++ b/drivers/gpu/nvgpu/gp106/sec2_gp106.c | |||
@@ -32,10 +32,6 @@ | |||
32 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> | 32 | #include <nvgpu/hw/gp106/hw_pwr_gp106.h> |
33 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> | 33 | #include <nvgpu/hw/gp106/hw_psec_gp106.h> |
34 | 34 | ||
35 | /*Defines*/ | ||
36 | #define gm20b_dbg_pmu(g, fmt, arg...) \ | ||
37 | nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg) | ||
38 | |||
39 | int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, | 35 | int gp106_sec2_clear_halt_interrupt_status(struct gk20a *g, |
40 | unsigned int timeout) | 36 | unsigned int timeout) |
41 | { | 37 | { |
@@ -61,7 +57,7 @@ int gp106_sec2_wait_for_halt(struct gk20a *g, unsigned int timeout) | |||
61 | 57 | ||
62 | g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, | 58 | g->acr.capabilities = nvgpu_flcn_mailbox_read(&g->sec2_flcn, |
63 | FALCON_MAILBOX_1); | 59 | FALCON_MAILBOX_1); |
64 | gm20b_dbg_pmu(g, "ACR capabilities %x\n", g->acr.capabilities); | 60 | nvgpu_pmu_dbg(g, "ACR capabilities %x\n", g->acr.capabilities); |
65 | data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); | 61 | data = nvgpu_flcn_mailbox_read(&g->sec2_flcn, FALCON_MAILBOX_0); |
66 | if (data) { | 62 | if (data) { |
67 | nvgpu_err(g, "ACR boot failed, err %x", data); | 63 | nvgpu_err(g, "ACR boot failed, err %x", data); |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index e66fcff6..8412092a 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -589,6 +589,15 @@ static const struct gpu_ops gp10b_ops = { | |||
589 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 589 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, |
590 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | 590 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, |
591 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 591 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
592 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | ||
593 | .pmu_isr = gk20a_pmu_isr, | ||
594 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | ||
595 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | ||
596 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | ||
597 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | ||
598 | .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, | ||
599 | .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, | ||
600 | .pmu_enable_irq = gk20a_pmu_enable_irq, | ||
592 | .write_dmatrfbase = gp10b_write_dmatrfbase, | 601 | .write_dmatrfbase = gp10b_write_dmatrfbase, |
593 | .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, | 602 | .pmu_elpg_statistics = gp10b_pmu_elpg_statistics, |
594 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, | 603 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon, |
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c index 9851fc5d..033d02c5 100644 --- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c | |||
@@ -128,7 +128,7 @@ void mc_gp10b_isr_stall(struct gk20a *g) | |||
128 | gk20a_fifo_isr(g); | 128 | gk20a_fifo_isr(g); |
129 | } | 129 | } |
130 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { | 130 | if ((mc_intr_0 & mc_intr_pmu_pending_f()) != 0U) { |
131 | gk20a_pmu_isr(g); | 131 | g->ops.pmu.pmu_isr(g); |
132 | } | 132 | } |
133 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { | 133 | if ((mc_intr_0 & mc_intr_priv_ring_pending_f()) != 0U) { |
134 | g->ops.priv_ring.isr(g); | 134 | g->ops.priv_ring.isr(g); |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 69ad018a..789fe8d9 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -732,6 +732,15 @@ static const struct gpu_ops gv100_ops = { | |||
732 | .pmu_queue_tail = gk20a_pmu_queue_tail, | 732 | .pmu_queue_tail = gk20a_pmu_queue_tail, |
733 | .pmu_get_queue_head = pwr_pmu_queue_head_r, | 733 | .pmu_get_queue_head = pwr_pmu_queue_head_r, |
734 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 734 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
735 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | ||
736 | .pmu_isr = gk20a_pmu_isr, | ||
737 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | ||
738 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | ||
739 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | ||
740 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | ||
741 | .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, | ||
742 | .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, | ||
743 | .pmu_enable_irq = gk20a_pmu_enable_irq, | ||
735 | .is_pmu_supported = gp106_is_pmu_supported, | 744 | .is_pmu_supported = gp106_is_pmu_supported, |
736 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, | 745 | .pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list, |
737 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | 746 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, |
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index a6bbaa40..e27c1760 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -37,7 +37,6 @@ | |||
37 | #include "gk20a/gk20a.h" | 37 | #include "gk20a/gk20a.h" |
38 | #include "acr_gv11b.h" | 38 | #include "acr_gv11b.h" |
39 | #include "pmu_gv11b.h" | 39 | #include "pmu_gv11b.h" |
40 | #include "gk20a/pmu_gk20a.h" | ||
41 | #include "gm20b/mm_gm20b.h" | 40 | #include "gm20b/mm_gm20b.h" |
42 | #include "gm20b/acr_gm20b.h" | 41 | #include "gm20b/acr_gm20b.h" |
43 | #include "gp106/acr_gp106.h" | 42 | #include "gp106/acr_gp106.h" |
@@ -287,7 +286,7 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g, | |||
287 | 286 | ||
288 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 287 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
289 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 288 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
290 | pmu_enable_irq(pmu, false); | 289 | g->ops.pmu.pmu_enable_irq(pmu, false); |
291 | pmu->isr_enabled = false; | 290 | pmu->isr_enabled = false; |
292 | nvgpu_mutex_release(&pmu->isr_mutex); | 291 | nvgpu_mutex_release(&pmu->isr_mutex); |
293 | /*Clearing mailbox register used to reflect capabilities*/ | 292 | /*Clearing mailbox register used to reflect capabilities*/ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index cf669aa7..a728d989 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -680,6 +680,15 @@ static const struct gpu_ops gv11b_ops = { | |||
680 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 680 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, |
681 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, | 681 | .pmu_mutex_acquire = gk20a_pmu_mutex_acquire, |
682 | .pmu_mutex_release = gk20a_pmu_mutex_release, | 682 | .pmu_mutex_release = gk20a_pmu_mutex_release, |
683 | .pmu_is_interrupted = gk20a_pmu_is_interrupted, | ||
684 | .pmu_isr = gk20a_pmu_isr, | ||
685 | .pmu_init_perfmon_counter = gk20a_pmu_init_perfmon_counter, | ||
686 | .pmu_pg_idle_counter_config = gk20a_pmu_pg_idle_counter_config, | ||
687 | .pmu_read_idle_counter = gk20a_pmu_read_idle_counter, | ||
688 | .pmu_reset_idle_counter = gk20a_pmu_reset_idle_counter, | ||
689 | .pmu_dump_elpg_stats = gk20a_pmu_dump_elpg_stats, | ||
690 | .pmu_dump_falcon_stats = gk20a_pmu_dump_falcon_stats, | ||
691 | .pmu_enable_irq = gk20a_pmu_enable_irq, | ||
683 | .write_dmatrfbase = gp10b_write_dmatrfbase, | 692 | .write_dmatrfbase = gp10b_write_dmatrfbase, |
684 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, | 693 | .pmu_elpg_statistics = gp106_pmu_elpg_statistics, |
685 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc, | 694 | .pmu_init_perfmon = nvgpu_pmu_init_perfmon_rpc, |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmu.h b/drivers/gpu/nvgpu/include/nvgpu/pmu.h index 1240530f..81abdb24 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmu.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmu.h | |||
@@ -512,5 +512,9 @@ int nvgpu_pmu_rpc_execute(struct nvgpu_pmu *pmu, struct nv_pmu_rpc_header *rpc, | |||
512 | u16 size_rpc, u16 size_scratch, pmu_callback callback, void *cb_param, | 512 | u16 size_rpc, u16 size_scratch, pmu_callback callback, void *cb_param, |
513 | bool is_copy_back); | 513 | bool is_copy_back); |
514 | 514 | ||
515 | /* PMU wait*/ | ||
516 | int pmu_wait_message_cond(struct nvgpu_pmu *pmu, u32 timeout_ms, | ||
517 | void *var, u8 val); | ||
518 | |||
515 | struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu); | 519 | struct gk20a *gk20a_from_pmu(struct nvgpu_pmu *pmu); |
516 | #endif /* NVGPU_PMU_H */ | 520 | #endif /* NVGPU_PMU_H */ |
diff --git a/drivers/gpu/nvgpu/os/linux/sysfs.c b/drivers/gpu/nvgpu/os/linux/sysfs.c index d0a29300..a42070d4 100644 --- a/drivers/gpu/nvgpu/os/linux/sysfs.c +++ b/drivers/gpu/nvgpu/os/linux/sysfs.c | |||
@@ -24,7 +24,6 @@ | |||
24 | 24 | ||
25 | #include "sysfs.h" | 25 | #include "sysfs.h" |
26 | #include "platform_gk20a.h" | 26 | #include "platform_gk20a.h" |
27 | #include "gk20a/pmu_gk20a.h" | ||
28 | #include "gk20a/gr_gk20a.h" | 27 | #include "gk20a/gr_gk20a.h" |
29 | #include "gv11b/gr_gv11b.h" | 28 | #include "gv11b/gr_gv11b.h" |
30 | 29 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 070339d2..3aa9b092 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -52,6 +52,7 @@ | |||
52 | #include "gk20a/flcn_gk20a.h" | 52 | #include "gk20a/flcn_gk20a.h" |
53 | #include "gk20a/mc_gk20a.h" | 53 | #include "gk20a/mc_gk20a.h" |
54 | #include "gk20a/dbg_gpu_gk20a.h" | 54 | #include "gk20a/dbg_gpu_gk20a.h" |
55 | #include "gk20a/pmu_gk20a.h" | ||
55 | 56 | ||
56 | #include "gp10b/mc_gp10b.h" | 57 | #include "gp10b/mc_gp10b.h" |
57 | #include "gp10b/mm_gp10b.h" | 58 | #include "gp10b/mm_gp10b.h" |
@@ -430,6 +431,15 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
430 | .pmu_mutex_size = NULL, | 431 | .pmu_mutex_size = NULL, |
431 | .pmu_mutex_acquire = NULL, | 432 | .pmu_mutex_acquire = NULL, |
432 | .pmu_mutex_release = NULL, | 433 | .pmu_mutex_release = NULL, |
434 | .pmu_is_interrupted = NULL, | ||
435 | .pmu_isr = NULL, | ||
436 | .pmu_init_perfmon_counter = NULL, | ||
437 | .pmu_pg_idle_counter_config = NULL, | ||
438 | .pmu_read_idle_counter = NULL, | ||
439 | .pmu_reset_idle_counter = NULL, | ||
440 | .pmu_dump_elpg_stats = NULL, | ||
441 | .pmu_dump_falcon_stats = NULL, | ||
442 | .pmu_enable_irq = NULL, | ||
433 | .write_dmatrfbase = NULL, | 443 | .write_dmatrfbase = NULL, |
434 | .pmu_elpg_statistics = NULL, | 444 | .pmu_elpg_statistics = NULL, |
435 | .pmu_init_perfmon = NULL, | 445 | .pmu_init_perfmon = NULL, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index 823da61a..44bcb123 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -57,6 +57,7 @@ | |||
57 | #include <gk20a/flcn_gk20a.h> | 57 | #include <gk20a/flcn_gk20a.h> |
58 | #include <gk20a/mc_gk20a.h> | 58 | #include <gk20a/mc_gk20a.h> |
59 | #include "gk20a/dbg_gpu_gk20a.h" | 59 | #include "gk20a/dbg_gpu_gk20a.h" |
60 | #include <gk20a/pmu_gk20a.h> | ||
60 | 61 | ||
61 | #include <gm20b/gr_gm20b.h> | 62 | #include <gm20b/gr_gm20b.h> |
62 | #include <gm20b/fifo_gm20b.h> | 63 | #include <gm20b/fifo_gm20b.h> |
@@ -495,6 +496,15 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
495 | .pmu_mutex_size = NULL, | 496 | .pmu_mutex_size = NULL, |
496 | .pmu_mutex_acquire = NULL, | 497 | .pmu_mutex_acquire = NULL, |
497 | .pmu_mutex_release = NULL, | 498 | .pmu_mutex_release = NULL, |
499 | .pmu_is_interrupted = NULL, | ||
500 | .pmu_isr = NULL, | ||
501 | .pmu_init_perfmon_counter = NULL, | ||
502 | .pmu_pg_idle_counter_config = NULL, | ||
503 | .pmu_read_idle_counter = NULL, | ||
504 | .pmu_reset_idle_counter = NULL, | ||
505 | .pmu_dump_elpg_stats = NULL, | ||
506 | .pmu_dump_falcon_stats = NULL, | ||
507 | .pmu_enable_irq = NULL, | ||
498 | .write_dmatrfbase = NULL, | 508 | .write_dmatrfbase = NULL, |
499 | .pmu_elpg_statistics = NULL, | 509 | .pmu_elpg_statistics = NULL, |
500 | .pmu_init_perfmon = NULL, | 510 | .pmu_init_perfmon = NULL, |