diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | 14 |
2 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 4aca3424..06b00a25 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -117,6 +117,8 @@ irqreturn_t mc_gk20a_intr_thread_nonstall(struct gk20a *g) | |||
117 | 117 | ||
118 | if (mc_intr_1 & mc_intr_0_pfifo_pending_f()) | 118 | if (mc_intr_1 & mc_intr_0_pfifo_pending_f()) |
119 | gk20a_fifo_nonstall_isr(g); | 119 | gk20a_fifo_nonstall_isr(g); |
120 | if (mc_intr_1 & mc_intr_0_priv_ring_pending_f()) | ||
121 | gk20a_priv_ring_isr(g); | ||
120 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) | 122 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_GR_GK20A].intr_id)) |
121 | gk20a_gr_nonstall_isr(g); | 123 | gk20a_gr_nonstall_isr(g); |
122 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) | 124 | if (mc_intr_1 & BIT(g->fifo.engine_info[ENGINE_CE2_GK20A].intr_id) |
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c index c893c681..f5aa3f0f 100644 --- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c | |||
@@ -66,13 +66,25 @@ void gk20a_priv_ring_isr(struct gk20a *g) | |||
66 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); | 66 | status0 = gk20a_readl(g, pri_ringmaster_intr_status0_r()); |
67 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); | 67 | status1 = gk20a_readl(g, pri_ringmaster_intr_status1_r()); |
68 | 68 | ||
69 | gk20a_dbg_info("ringmaster intr status0: 0x%08x," | 69 | gk20a_dbg(gpu_dbg_intr, "ringmaster intr status0: 0x%08x," |
70 | "status1: 0x%08x", status0, status1); | 70 | "status1: 0x%08x", status0, status1); |
71 | 71 | ||
72 | if (status0 & (0x1 | 0x2 | 0x4)) { | 72 | if (status0 & (0x1 | 0x2 | 0x4)) { |
73 | gk20a_reset_priv_ring(g); | 73 | gk20a_reset_priv_ring(g); |
74 | } | 74 | } |
75 | 75 | ||
76 | if (status0 & 0x100) { | ||
77 | gk20a_dbg(gpu_dbg_intr, "SYS write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | ||
78 | gk20a_readl(g, 0x122120), gk20a_readl(g, 0x122124), gk20a_readl(g, 0x122128), | ||
79 | gk20a_readl(g, 0x12212c)); | ||
80 | } | ||
81 | |||
82 | if (status1 & 0x1) { | ||
83 | gk20a_dbg(gpu_dbg_intr, "GPC write error. ADR %08x WRDAT %08x INFO %08x, CODE %08x", | ||
84 | gk20a_readl(g, 0x128120), gk20a_readl(g, 0x128124), gk20a_readl(g, 0x128128), | ||
85 | gk20a_readl(g, 0x12812c)); | ||
86 | } | ||
87 | |||
76 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); | 88 | cmd = gk20a_readl(g, pri_ringmaster_command_r()); |
77 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), | 89 | cmd = set_field(cmd, pri_ringmaster_command_cmd_m(), |
78 | pri_ringmaster_command_cmd_ack_interrupt_f()); | 90 | pri_ringmaster_command_cmd_ack_interrupt_f()); |