diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.sources | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/top/top_gv100.c | 66 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/top/top_gv100.h | 37 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/nvlink_gv100.c | 25 |
7 files changed, 138 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile index 3b6a022a..778d46fc 100644 --- a/drivers/gpu/nvgpu/Makefile +++ b/drivers/gpu/nvgpu/Makefile | |||
@@ -44,7 +44,8 @@ nvgpu-y += common/bus/bus_gk20a.o \ | |||
44 | common/therm/therm_gv11b.o \ | 44 | common/therm/therm_gv11b.o \ |
45 | common/fuse/fuse_gm20b.o \ | 45 | common/fuse/fuse_gm20b.o \ |
46 | common/fuse/fuse_gp10b.o \ | 46 | common/fuse/fuse_gp10b.o \ |
47 | common/fuse/fuse_gp106.o | 47 | common/fuse/fuse_gp106.o \ |
48 | common/top/top_gv100.o | ||
48 | 49 | ||
49 | # Linux specific parts of nvgpu. | 50 | # Linux specific parts of nvgpu. |
50 | nvgpu-y += \ | 51 | nvgpu-y += \ |
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources index 7dc0251b..b96ce719 100644 --- a/drivers/gpu/nvgpu/Makefile.sources +++ b/drivers/gpu/nvgpu/Makefile.sources | |||
@@ -77,6 +77,7 @@ srcs := os/posix/nvgpu.c \ | |||
77 | common/fuse/fuse_gm20b.c \ | 77 | common/fuse/fuse_gm20b.c \ |
78 | common/fuse/fuse_gp10b.c \ | 78 | common/fuse/fuse_gp10b.c \ |
79 | common/fuse/fuse_gp106.c \ | 79 | common/fuse/fuse_gp106.c \ |
80 | common/top/top_gv100.c \ | ||
80 | common/enabled.c \ | 81 | common/enabled.c \ |
81 | common/pramin.c \ | 82 | common/pramin.c \ |
82 | common/semaphore.c \ | 83 | common/semaphore.c \ |
diff --git a/drivers/gpu/nvgpu/common/top/top_gv100.c b/drivers/gpu/nvgpu/common/top/top_gv100.c new file mode 100644 index 00000000..138528a2 --- /dev/null +++ b/drivers/gpu/nvgpu/common/top/top_gv100.c | |||
@@ -0,0 +1,66 @@ | |||
1 | /* | ||
2 | * GV100 TOP UNIT | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #include <nvgpu/io.h> | ||
26 | |||
27 | #include "gk20a/gk20a.h" | ||
28 | #include "top_gv100.h" | ||
29 | |||
30 | #include <nvgpu/hw/gv100/hw_top_gv100.h> | ||
31 | |||
32 | u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g) | ||
33 | { | ||
34 | u32 reg; | ||
35 | |||
36 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
37 | return top_nvhsclk_ctrl_e_clk_nvl_v(reg); | ||
38 | } | ||
39 | |||
40 | void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val) | ||
41 | { | ||
42 | u32 reg; | ||
43 | |||
44 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
45 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | ||
46 | top_nvhsclk_ctrl_e_clk_nvl_f(val)); | ||
47 | nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg); | ||
48 | } | ||
49 | |||
50 | u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g) | ||
51 | { | ||
52 | u32 reg; | ||
53 | |||
54 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
55 | return top_nvhsclk_ctrl_swap_clk_nvl_v(reg); | ||
56 | } | ||
57 | |||
58 | void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val) | ||
59 | { | ||
60 | u32 reg; | ||
61 | |||
62 | reg = nvgpu_readl(g, top_nvhsclk_ctrl_r()); | ||
63 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | ||
64 | top_nvhsclk_ctrl_swap_clk_nvl_f(val)); | ||
65 | nvgpu_writel(g, top_nvhsclk_ctrl_r(), reg); | ||
66 | } | ||
diff --git a/drivers/gpu/nvgpu/common/top/top_gv100.h b/drivers/gpu/nvgpu/common/top/top_gv100.h new file mode 100644 index 00000000..885b7814 --- /dev/null +++ b/drivers/gpu/nvgpu/common/top/top_gv100.h | |||
@@ -0,0 +1,37 @@ | |||
1 | /* | ||
2 | * GV100 TOP UNIT | ||
3 | * | ||
4 | * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. | ||
5 | * | ||
6 | * Permission is hereby granted, free of charge, to any person obtaining a | ||
7 | * copy of this software and associated documentation files (the "Software"), | ||
8 | * to deal in the Software without restriction, including without limitation | ||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | ||
10 | * and/or sell copies of the Software, and to permit persons to whom the | ||
11 | * Software is furnished to do so, subject to the following conditions: | ||
12 | * | ||
13 | * The above copyright notice and this permission notice shall be included in | ||
14 | * all copies or substantial portions of the Software. | ||
15 | * | ||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | ||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | ||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | ||
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | ||
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | ||
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | ||
22 | * DEALINGS IN THE SOFTWARE. | ||
23 | */ | ||
24 | |||
25 | #ifndef TOP_GV100_H | ||
26 | #define TOP_GV100_H | ||
27 | |||
28 | #include <nvgpu/types.h> | ||
29 | |||
30 | struct gk20a; | ||
31 | |||
32 | u32 gv100_top_get_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g); | ||
33 | void gv100_top_set_nvhsclk_ctrl_e_clk_nvl(struct gk20a *g, u32 val); | ||
34 | u32 gv100_top_get_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g); | ||
35 | void gv100_top_set_nvhsclk_ctrl_swap_clk_nvl(struct gk20a *g, u32 val); | ||
36 | |||
37 | #endif | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 03510a16..89a05b3c 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1314,7 +1314,12 @@ struct gpu_ops { | |||
1314 | int (*shutdown)(struct gk20a *g); | 1314 | int (*shutdown)(struct gk20a *g); |
1315 | int (*early_init)(struct gk20a *g); | 1315 | int (*early_init)(struct gk20a *g); |
1316 | } nvlink; | 1316 | } nvlink; |
1317 | 1317 | struct { | |
1318 | u32 (*get_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g); | ||
1319 | void (*set_nvhsclk_ctrl_e_clk_nvl)(struct gk20a *g, u32 val); | ||
1320 | u32 (*get_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g); | ||
1321 | void (*set_nvhsclk_ctrl_swap_clk_nvl)(struct gk20a *g, u32 val); | ||
1322 | } top; | ||
1318 | void (*semaphore_wakeup)(struct gk20a *g, bool post_events); | 1323 | void (*semaphore_wakeup)(struct gk20a *g, bool post_events); |
1319 | }; | 1324 | }; |
1320 | 1325 | ||
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 9d90d1d4..589f6adf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -44,6 +44,7 @@ | |||
44 | #include "common/fuse/fuse_gm20b.h" | 44 | #include "common/fuse/fuse_gm20b.h" |
45 | #include "common/fuse/fuse_gp10b.h" | 45 | #include "common/fuse/fuse_gp10b.h" |
46 | #include "common/fuse/fuse_gp106.h" | 46 | #include "common/fuse/fuse_gp106.h" |
47 | #include "common/top/top_gv100.h" | ||
47 | 48 | ||
48 | #include "gk20a/gk20a.h" | 49 | #include "gk20a/gk20a.h" |
49 | #include "gk20a/fifo_gk20a.h" | 50 | #include "gk20a/fifo_gk20a.h" |
@@ -926,6 +927,16 @@ static const struct gpu_ops gv100_ops = { | |||
926 | .early_init = gv100_nvlink_early_init, | 927 | .early_init = gv100_nvlink_early_init, |
927 | }, | 928 | }, |
928 | #endif | 929 | #endif |
930 | .top = { | ||
931 | .get_nvhsclk_ctrl_e_clk_nvl = | ||
932 | gv100_top_get_nvhsclk_ctrl_e_clk_nvl, | ||
933 | .set_nvhsclk_ctrl_e_clk_nvl = | ||
934 | gv100_top_set_nvhsclk_ctrl_e_clk_nvl, | ||
935 | .get_nvhsclk_ctrl_swap_clk_nvl = | ||
936 | gv100_top_get_nvhsclk_ctrl_swap_clk_nvl, | ||
937 | .set_nvhsclk_ctrl_swap_clk_nvl = | ||
938 | gv100_top_set_nvhsclk_ctrl_swap_clk_nvl, | ||
939 | }, | ||
929 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, | 940 | .chip_init_gpu_characteristics = gv100_init_gpu_characteristics, |
930 | .get_litter_value = gv100_get_litter_value, | 941 | .get_litter_value = gv100_get_litter_value, |
931 | }; | 942 | }; |
@@ -964,6 +975,7 @@ int gv100_init_hal(struct gk20a *g) | |||
964 | gops->priv_ring = gv100_ops.priv_ring; | 975 | gops->priv_ring = gv100_ops.priv_ring; |
965 | gops->fuse = gv100_ops.fuse; | 976 | gops->fuse = gv100_ops.fuse; |
966 | gops->nvlink = gv100_ops.nvlink; | 977 | gops->nvlink = gv100_ops.nvlink; |
978 | gops->top = gv100_ops.top; | ||
967 | 979 | ||
968 | /* clocks */ | 980 | /* clocks */ |
969 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; | 981 | gops->clk.init_clk_support = gv100_ops.clk.init_clk_support; |
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c index 3e1b2cda..7457c181 100644 --- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c +++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c | |||
@@ -1461,7 +1461,8 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1461 | u32 i; | 1461 | u32 i; |
1462 | u32 links_off; | 1462 | u32 links_off; |
1463 | struct nvgpu_timeout timeout; | 1463 | struct nvgpu_timeout timeout; |
1464 | u32 pad_ctrl, swap_ctrl; | 1464 | u32 pad_ctrl = 0; |
1465 | u32 swap_ctrl = 0; | ||
1465 | u32 pll_id; | 1466 | u32 pll_id; |
1466 | 1467 | ||
1467 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); | 1468 | reg = gk20a_readl(g, trim_sys_nvlink_uphy_cfg_r()); |
@@ -1469,10 +1470,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1469 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); | 1470 | trim_sys_nvlink_uphy_cfg_phy2clks_use_lockdet_f(1)); |
1470 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); | 1471 | gk20a_writel(g, trim_sys_nvlink_uphy_cfg_r(), reg); |
1471 | 1472 | ||
1472 | reg = gk20a_readl(g, top_nvhsclk_ctrl_r()); | 1473 | if (g->ops.top.get_nvhsclk_ctrl_e_clk_nvl) { |
1473 | 1474 | pad_ctrl = g->ops.top.get_nvhsclk_ctrl_e_clk_nvl(g); | |
1474 | pad_ctrl = top_nvhsclk_ctrl_e_clk_nvl_v(reg); | 1475 | } |
1475 | swap_ctrl = top_nvhsclk_ctrl_swap_clk_nvl_v(reg); | 1476 | if (g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl) { |
1477 | swap_ctrl = g->ops.top.get_nvhsclk_ctrl_swap_clk_nvl(g); | ||
1478 | } | ||
1476 | 1479 | ||
1477 | for_each_set_bit(i, &link_mask, 32) { | 1480 | for_each_set_bit(i, &link_mask, 32) { |
1478 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. | 1481 | /* There are 3 PLLs for 6 links. We have 3 bits for each PLL. |
@@ -1483,12 +1486,12 @@ int gv100_nvlink_setup_pll(struct gk20a *g, unsigned long link_mask) | |||
1483 | swap_ctrl |= BIT(pll_id); | 1486 | swap_ctrl |= BIT(pll_id); |
1484 | } | 1487 | } |
1485 | 1488 | ||
1486 | reg = set_field(reg, top_nvhsclk_ctrl_e_clk_nvl_m(), | 1489 | if (g->ops.top.set_nvhsclk_ctrl_e_clk_nvl) { |
1487 | top_nvhsclk_ctrl_e_clk_nvl_f(pad_ctrl)); | 1490 | g->ops.top.set_nvhsclk_ctrl_e_clk_nvl(g, pad_ctrl); |
1488 | reg = set_field(reg, top_nvhsclk_ctrl_swap_clk_nvl_m(), | 1491 | } |
1489 | top_nvhsclk_ctrl_swap_clk_nvl_f(swap_ctrl)); | 1492 | if (g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl) { |
1490 | 1493 | g->ops.top.set_nvhsclk_ctrl_swap_clk_nvl(g, swap_ctrl); | |
1491 | gk20a_writel(g, top_nvhsclk_ctrl_r(), reg); | 1494 | } |
1492 | 1495 | ||
1493 | for_each_set_bit(i, &link_mask, 32) { | 1496 | for_each_set_bit(i, &link_mask, 32) { |
1494 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); | 1497 | reg = gk20a_readl(g, TRIM_SYS_NVLINK_CTRL(i)); |