diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/Makefile.nvgpu-t18x | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.c | 70 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/pmu_gp106.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.c | 158 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/lpwr/rppg.h | 17 |
7 files changed, 250 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x index 9e08e2c6..2b650ad8 100644 --- a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x +++ b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x | |||
@@ -62,7 +62,8 @@ nvgpu-y += \ | |||
62 | $(nvgpu-t18x)/therm/thrm.o \ | 62 | $(nvgpu-t18x)/therm/thrm.o \ |
63 | $(nvgpu-t18x)/therm/thrmdev.o \ | 63 | $(nvgpu-t18x)/therm/thrmdev.o \ |
64 | $(nvgpu-t18x)/therm/thrmchannel.o \ | 64 | $(nvgpu-t18x)/therm/thrmchannel.o \ |
65 | $(nvgpu-t18x)/therm/thrmpmu.o | 65 | $(nvgpu-t18x)/therm/thrmpmu.o \ |
66 | $(nvgpu-t18x)/lpwr/rppg.o | ||
66 | 67 | ||
67 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o | 68 | nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o |
68 | 69 | ||
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.c b/drivers/gpu/nvgpu/gp106/pmu_gp106.c index 6db80abe..6f5e71eb 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.c +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include "clk/clk_mclk.h" | 24 | #include "clk/clk_mclk.h" |
25 | #include "hw_mc_gp106.h" | 25 | #include "hw_mc_gp106.h" |
26 | #include "hw_pwr_gp106.h" | 26 | #include "hw_pwr_gp106.h" |
27 | #include "lpwr/rppg.h" | ||
27 | 28 | ||
28 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 | 29 | #define PMU_MEM_SCRUBBING_TIMEOUT_MAX 1000 |
29 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 | 30 | #define PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT 10 |
@@ -174,6 +175,67 @@ static bool gp106_is_pmu_supported(struct gk20a *g) | |||
174 | return true; | 175 | return true; |
175 | } | 176 | } |
176 | 177 | ||
178 | static u32 gp106_pmu_pg_feature_list(struct gk20a *g, u32 pg_engine_id) | ||
179 | { | ||
180 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | ||
181 | return PMU_PG_FEATURE_GR_RPPG_ENABLED; | ||
182 | |||
183 | return 0; | ||
184 | } | ||
185 | |||
186 | static u32 gp106_pmu_pg_engines_list(struct gk20a *g) | ||
187 | { | ||
188 | return BIT(PMU_PG_ELPG_ENGINE_ID_GRAPHICS); | ||
189 | } | ||
190 | |||
191 | static void pmu_handle_param_msg(struct gk20a *g, struct pmu_msg *msg, | ||
192 | void *param, u32 handle, u32 status) | ||
193 | { | ||
194 | gk20a_dbg_fn(""); | ||
195 | |||
196 | if (status != 0) { | ||
197 | gk20a_err(dev_from_gk20a(g), "PG PARAM cmd aborted"); | ||
198 | return; | ||
199 | } | ||
200 | |||
201 | gp106_dbg_pmu("PG PARAM is acknowledged from PMU %x", | ||
202 | msg->msg.pg.msg_type); | ||
203 | } | ||
204 | |||
205 | static int gp106_pg_param_init(struct gk20a *g, u32 pg_engine_id) | ||
206 | { | ||
207 | struct pmu_gk20a *pmu = &g->pmu; | ||
208 | struct pmu_cmd cmd; | ||
209 | u32 seq; | ||
210 | u32 status; | ||
211 | |||
212 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
213 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { | ||
214 | |||
215 | status = init_rppg(g); | ||
216 | if (status != 0) { | ||
217 | gk20a_err(dev_from_gk20a(g), "RPPG init Failed"); | ||
218 | return -1; | ||
219 | } | ||
220 | |||
221 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
222 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
223 | sizeof(struct pmu_pg_cmd_gr_init_param); | ||
224 | cmd.cmd.pg.gr_init_param.cmd_type = | ||
225 | PMU_PG_CMD_ID_PG_PARAM; | ||
226 | cmd.cmd.pg.gr_init_param.sub_cmd_id = | ||
227 | PMU_PG_PARAM_CMD_GR_INIT_PARAM; | ||
228 | cmd.cmd.pg.gr_init_param.featuremask = | ||
229 | PMU_PG_FEATURE_GR_RPPG_ENABLED; | ||
230 | |||
231 | gp106_dbg_pmu("cmd post GR PMU_PG_CMD_ID_PG_PARAM"); | ||
232 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
233 | pmu_handle_param_msg, pmu, &seq, ~0); | ||
234 | } | ||
235 | |||
236 | return 0; | ||
237 | } | ||
238 | |||
177 | void gp106_init_pmu_ops(struct gpu_ops *gops) | 239 | void gp106_init_pmu_ops(struct gpu_ops *gops) |
178 | { | 240 | { |
179 | gk20a_dbg_fn(""); | 241 | gk20a_dbg_fn(""); |
@@ -195,10 +257,10 @@ void gp106_init_pmu_ops(struct gpu_ops *gops) | |||
195 | gops->pmu.lspmuwprinitdone = 0; | 257 | gops->pmu.lspmuwprinitdone = 0; |
196 | gops->pmu.fecsbootstrapdone = false; | 258 | gops->pmu.fecsbootstrapdone = false; |
197 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; | 259 | gops->pmu.write_dmatrfbase = gp10b_write_dmatrfbase; |
198 | gops->pmu.pmu_elpg_statistics = NULL; | 260 | gops->pmu.pmu_elpg_statistics = gp10b_pmu_elpg_statistics; |
199 | gops->pmu.pmu_pg_init_param = NULL; | 261 | gops->pmu.pmu_pg_init_param = gp106_pg_param_init; |
200 | gops->pmu.pmu_pg_supported_engines_list = NULL; | 262 | gops->pmu.pmu_pg_supported_engines_list = gp106_pmu_pg_engines_list; |
201 | gops->pmu.pmu_pg_engines_feature_list = NULL; | 263 | gops->pmu.pmu_pg_engines_feature_list = gp106_pmu_pg_feature_list; |
202 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; | 264 | gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; |
203 | gops->pmu.dump_secure_fuses = NULL; | 265 | gops->pmu.dump_secure_fuses = NULL; |
204 | gops->pmu.reset = gp106_falcon_reset; | 266 | gops->pmu.reset = gp106_falcon_reset; |
diff --git a/drivers/gpu/nvgpu/gp106/pmu_gp106.h b/drivers/gpu/nvgpu/gp106/pmu_gp106.h index 8fb4c736..a42ff620 100644 --- a/drivers/gpu/nvgpu/gp106/pmu_gp106.h +++ b/drivers/gpu/nvgpu/gp106/pmu_gp106.h | |||
@@ -14,6 +14,9 @@ | |||
14 | #ifndef __PMU_GP106_H_ | 14 | #ifndef __PMU_GP106_H_ |
15 | #define __PMU_GP106_H_ | 15 | #define __PMU_GP106_H_ |
16 | 16 | ||
17 | #define gp106_dbg_pmu(fmt, arg...) \ | ||
18 | gk20a_dbg(gpu_dbg_pmu, fmt, ##arg) | ||
19 | |||
17 | void gp106_init_pmu_ops(struct gpu_ops *gops); | 20 | void gp106_init_pmu_ops(struct gpu_ops *gops); |
18 | 21 | ||
19 | #endif /*__PMU_GP106_H_*/ | 22 | #endif /*__PMU_GP106_H_*/ |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c index b5fdf2fd..cd9cd0b0 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.c | |||
@@ -249,7 +249,8 @@ int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id) | |||
249 | 249 | ||
250 | return 0; | 250 | return 0; |
251 | } | 251 | } |
252 | static void gp10b_pmu_elpg_statistics(struct gk20a *g, | 252 | |
253 | void gp10b_pmu_elpg_statistics(struct gk20a *g, | ||
253 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) | 254 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt) |
254 | { | 255 | { |
255 | struct pmu_gk20a *pmu = &g->pmu; | 256 | struct pmu_gk20a *pmu = &g->pmu; |
diff --git a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h index 30245554..ee0158ec 100644 --- a/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h +++ b/drivers/gpu/nvgpu/gp10b/pmu_gp10b.h | |||
@@ -20,5 +20,7 @@ void gp10b_init_pmu_ops(struct gpu_ops *gops); | |||
20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); | 20 | int gp10b_load_falcon_ucode(struct gk20a *g, u32 falconidmask); |
21 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); | 21 | int gp10b_pg_gr_init(struct gk20a *g, u32 pg_engine_id); |
22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); | 22 | void gp10b_write_dmatrfbase(struct gk20a *g, u32 addr); |
23 | void gp10b_pmu_elpg_statistics(struct gk20a *g, | ||
24 | u32 *ingating_time, u32 *ungating_time, u32 *gating_cnt); | ||
23 | 25 | ||
24 | #endif /*__PMU_GP10B_H_*/ | 26 | #endif /*__PMU_GP10B_H_*/ |
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c new file mode 100644 index 00000000..40e857ee --- /dev/null +++ b/drivers/gpu/nvgpu/lpwr/rppg.c | |||
@@ -0,0 +1,158 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #include "gk20a/gk20a.h" | ||
15 | #include "gk20a/pmu_gk20a.h" | ||
16 | #include "gp106/pmu_gp106.h" | ||
17 | #include "gk20a/pmu_api.h" | ||
18 | #include "gm206/bios_gm206.h" | ||
19 | #include "pstate/pstate.h" | ||
20 | #include "include/bios.h" | ||
21 | #include "pmuif/gpmuif_pg_rppg.h" | ||
22 | |||
23 | static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, | ||
24 | void *param, u32 handle, u32 status) | ||
25 | { | ||
26 | |||
27 | u8 ctrlId = NV_PMU_RPPG_CTRL_ID_MAX; | ||
28 | u32 *success = param; | ||
29 | |||
30 | if (status == 0) { | ||
31 | switch (msg->msg.pg.rppg_msg.cmn.msg_id) { | ||
32 | case NV_PMU_RPPG_MSG_ID_INIT_CTRL_ACK: | ||
33 | ctrlId = msg->msg.pg.rppg_msg.init_ctrl_ack.ctrl_id; | ||
34 | *success = 1; | ||
35 | gp106_dbg_pmu("RPPG is acknowledged from PMU %x", | ||
36 | msg->msg.pg.msg_type); | ||
37 | break; | ||
38 | } | ||
39 | } | ||
40 | |||
41 | gp106_dbg_pmu("RPPG is acknowledged from PMU %x", | ||
42 | msg->msg.pg.msg_type); | ||
43 | } | ||
44 | |||
45 | static u32 rppg_send_cmd(struct gk20a *g, struct nv_pmu_rppg_cmd *prppg_cmd) | ||
46 | { | ||
47 | struct pmu_cmd cmd; | ||
48 | u32 seq; | ||
49 | u32 status = 0; | ||
50 | u32 success = 0; | ||
51 | |||
52 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | ||
53 | cmd.hdr.unit_id = PMU_UNIT_PG; | ||
54 | cmd.hdr.size = PMU_CMD_HDR_SIZE + | ||
55 | sizeof(struct nv_pmu_rppg_cmd); | ||
56 | |||
57 | cmd.cmd.pg.rppg_cmd.cmn.cmd_type = PMU_PMU_PG_CMD_ID_RPPG; | ||
58 | cmd.cmd.pg.rppg_cmd.cmn.cmd_id = prppg_cmd->cmn.cmd_id; | ||
59 | |||
60 | switch (prppg_cmd->cmn.cmd_id) { | ||
61 | case NV_PMU_RPPG_CMD_ID_INIT: | ||
62 | break; | ||
63 | case NV_PMU_RPPG_CMD_ID_INIT_CTRL: | ||
64 | cmd.cmd.pg.rppg_cmd.init_ctrl.ctrl_id = | ||
65 | prppg_cmd->init_ctrl.ctrl_id; | ||
66 | cmd.cmd.pg.rppg_cmd.init_ctrl.domain_id = | ||
67 | prppg_cmd->init_ctrl.domain_id; | ||
68 | break; | ||
69 | case NV_PMU_RPPG_CMD_ID_STATS_RESET: | ||
70 | cmd.cmd.pg.rppg_cmd.stats_reset.ctrl_id = | ||
71 | prppg_cmd->stats_reset.ctrl_id; | ||
72 | break; | ||
73 | default: | ||
74 | gk20a_err(dev_from_gk20a(g), "Inivalid RPPG command %d", | ||
75 | prppg_cmd->cmn.cmd_id); | ||
76 | return -1; | ||
77 | } | ||
78 | |||
79 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, | ||
80 | pmu_handle_rppg_init_msg, &success, &seq, ~0); | ||
81 | if (status) { | ||
82 | gk20a_err(dev_from_gk20a(g), "Unable to submit parameter command %d", | ||
83 | prppg_cmd->cmn.cmd_id); | ||
84 | goto exit; | ||
85 | } | ||
86 | |||
87 | if (prppg_cmd->cmn.cmd_id == NV_PMU_RPPG_CMD_ID_INIT_CTRL) { | ||
88 | pmu_wait_message_cond(&g->pmu, gk20a_get_gr_idle_timeout(g), | ||
89 | &success, 1); | ||
90 | if (success == 0) { | ||
91 | status = -EINVAL; | ||
92 | gk20a_err(dev_from_gk20a(g), "Ack for the parameter command %x", | ||
93 | prppg_cmd->cmn.cmd_id); | ||
94 | } | ||
95 | } | ||
96 | |||
97 | exit: | ||
98 | return status; | ||
99 | } | ||
100 | |||
101 | static u32 rppg_init(struct gk20a *g) | ||
102 | { | ||
103 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
104 | |||
105 | rppg_cmd.init.cmd_id = NV_PMU_RPPG_CMD_ID_INIT; | ||
106 | |||
107 | return rppg_send_cmd(g, &rppg_cmd); | ||
108 | } | ||
109 | |||
110 | static u32 rppg_ctrl_init(struct gk20a *g, u8 ctrl_id) | ||
111 | { | ||
112 | struct nv_pmu_rppg_cmd rppg_cmd; | ||
113 | |||
114 | rppg_cmd.init_ctrl.cmd_id = NV_PMU_RPPG_CMD_ID_INIT_CTRL; | ||
115 | rppg_cmd.init_ctrl.ctrl_id = ctrl_id; | ||
116 | |||
117 | switch (ctrl_id) { | ||
118 | case NV_PMU_RPPG_CTRL_ID_GR: | ||
119 | case NV_PMU_RPPG_CTRL_ID_MS: | ||
120 | rppg_cmd.init_ctrl.domain_id = NV_PMU_RPPG_DOMAIN_ID_GFX; | ||
121 | break; | ||
122 | } | ||
123 | |||
124 | return rppg_send_cmd(g, &rppg_cmd); | ||
125 | } | ||
126 | |||
127 | u32 init_rppg(struct gk20a *g) | ||
128 | { | ||
129 | u32 status; | ||
130 | |||
131 | status = rppg_init(g); | ||
132 | if (status != 0) { | ||
133 | gk20a_err(dev_from_gk20a(g), | ||
134 | "Failed to initialize RPPG in PMU: 0x%08x", status); | ||
135 | return status; | ||
136 | } | ||
137 | |||
138 | |||
139 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_GR); | ||
140 | if (status != 0) { | ||
141 | gk20a_err(dev_from_gk20a(g), | ||
142 | "Failed to initialize RPPG_CTRL: GR in PMU: 0x%08x", | ||
143 | status); | ||
144 | return status; | ||
145 | } | ||
146 | |||
147 | status = rppg_ctrl_init(g, NV_PMU_RPPG_CTRL_ID_MS); | ||
148 | if (status != 0) { | ||
149 | gk20a_err(dev_from_gk20a(g), | ||
150 | "Failed to initialize RPPG_CTRL: MS in PMU: 0x%08x", | ||
151 | status); | ||
152 | return status; | ||
153 | } | ||
154 | |||
155 | return status; | ||
156 | } | ||
157 | |||
158 | |||
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.h b/drivers/gpu/nvgpu/lpwr/rppg.h new file mode 100644 index 00000000..8dc8d36c --- /dev/null +++ b/drivers/gpu/nvgpu/lpwr/rppg.h | |||
@@ -0,0 +1,17 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | #ifndef _RPPG_H_ | ||
14 | #define _RPPG_H_ | ||
15 | |||
16 | u32 init_rppg(struct gk20a *g); | ||
17 | #endif | ||