diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.c | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/acr_gv11b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 3 |
8 files changed, 63 insertions, 41 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 33d40cd5..e586913e 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -866,6 +866,8 @@ struct gpu_ops { | |||
866 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); | 866 | void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid); |
867 | void (*handle_ext_irq)(struct gk20a *g, u32 intr); | 867 | void (*handle_ext_irq)(struct gk20a *g, u32 intr); |
868 | void (*set_irqmask)(struct gk20a *g); | 868 | void (*set_irqmask)(struct gk20a *g); |
869 | void (*update_lspmu_cmdline_args)(struct gk20a *g); | ||
870 | void (*setup_apertures)(struct gk20a *g); | ||
869 | } pmu; | 871 | } pmu; |
870 | struct { | 872 | struct { |
871 | int (*init_debugfs)(struct gk20a *g); | 873 | int (*init_debugfs)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 09908df3..62d3a8fa 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1233,20 +1233,8 @@ int gm20b_init_nspmu_setup_hw1(struct gk20a *g) | |||
1233 | return err; | 1233 | return err; |
1234 | } | 1234 | } |
1235 | 1235 | ||
1236 | int gm20b_init_pmu_setup_hw1(struct gk20a *g, | 1236 | void gm20b_setup_apertures(struct gk20a *g) |
1237 | void *desc, u32 bl_sz) | ||
1238 | { | 1237 | { |
1239 | |||
1240 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1241 | int err; | ||
1242 | |||
1243 | gk20a_dbg_fn(""); | ||
1244 | |||
1245 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
1246 | nvgpu_flcn_reset(pmu->flcn); | ||
1247 | pmu->isr_enabled = true; | ||
1248 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
1249 | |||
1250 | /* setup apertures - virtual */ | 1238 | /* setup apertures - virtual */ |
1251 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 1239 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |
1252 | pwr_fbif_transcfg_mem_type_physical_f() | | 1240 | pwr_fbif_transcfg_mem_type_physical_f() | |
@@ -1263,10 +1251,14 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1263 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | 1251 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), |
1264 | pwr_fbif_transcfg_mem_type_physical_f() | | 1252 | pwr_fbif_transcfg_mem_type_physical_f() | |
1265 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | 1253 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); |
1254 | } | ||
1266 | 1255 | ||
1256 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g) | ||
1257 | { | ||
1258 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1267 | /*Copying pmu cmdline args*/ | 1259 | /*Copying pmu cmdline args*/ |
1268 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | 1260 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, |
1269 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); | 1261 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); |
1270 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | 1262 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); |
1271 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | 1263 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( |
1272 | pmu, GK20A_PMU_TRACE_BUFSIZE); | 1264 | pmu, GK20A_PMU_TRACE_BUFSIZE); |
@@ -1274,8 +1266,29 @@ int gm20b_init_pmu_setup_hw1(struct gk20a *g, | |||
1274 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | 1266 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( |
1275 | pmu, GK20A_PMU_DMAIDX_VIRT); | 1267 | pmu, GK20A_PMU_DMAIDX_VIRT); |
1276 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | 1268 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, |
1277 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | 1269 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), |
1278 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | 1270 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); |
1271 | } | ||
1272 | |||
1273 | int gm20b_init_pmu_setup_hw1(struct gk20a *g, | ||
1274 | void *desc, u32 bl_sz) | ||
1275 | { | ||
1276 | |||
1277 | struct nvgpu_pmu *pmu = &g->pmu; | ||
1278 | int err; | ||
1279 | |||
1280 | gk20a_dbg_fn(""); | ||
1281 | |||
1282 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
1283 | nvgpu_flcn_reset(pmu->flcn); | ||
1284 | pmu->isr_enabled = true; | ||
1285 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
1286 | |||
1287 | if (g->ops.pmu.setup_apertures) | ||
1288 | g->ops.pmu.setup_apertures(g); | ||
1289 | if (g->ops.pmu.update_lspmu_cmdline_args) | ||
1290 | g->ops.pmu.update_lspmu_cmdline_args(g); | ||
1291 | |||
1279 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 1292 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
1280 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 1293 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
1281 | pmu_enable_irq(pmu, false); | 1294 | pmu_enable_irq(pmu, false); |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 9d261aae..e22da730 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -47,6 +47,8 @@ int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g, | |||
47 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms); | 47 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms); |
48 | int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); | 48 | int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); |
49 | int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); | 49 | int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz); |
50 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g); | ||
51 | void gm20b_setup_apertures(struct gk20a *g); | ||
50 | 52 | ||
51 | int gm20b_pmu_setup_sw(struct gk20a *g); | 53 | int gm20b_pmu_setup_sw(struct gk20a *g); |
52 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); | 54 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 779dde3d..920a3e9b 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -660,6 +660,9 @@ int gm20b_init_hal(struct gk20a *g) | |||
660 | gops->pmu.falcon_clear_halt_interrupt_status = | 660 | gops->pmu.falcon_clear_halt_interrupt_status = |
661 | clear_halt_interrupt_status; | 661 | clear_halt_interrupt_status; |
662 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1; | 662 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1; |
663 | gops->pmu.update_lspmu_cmdline_args = | ||
664 | gm20b_update_lspmu_cmdline_args; | ||
665 | gops->pmu.setup_apertures = gm20b_setup_apertures; | ||
663 | 666 | ||
664 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 667 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
665 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | 668 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 335eb465..f13c2735 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -689,6 +689,9 @@ int gp10b_init_hal(struct gk20a *g) | |||
689 | gops->pmu.falcon_clear_halt_interrupt_status = | 689 | gops->pmu.falcon_clear_halt_interrupt_status = |
690 | clear_halt_interrupt_status, | 690 | clear_halt_interrupt_status, |
691 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, | 691 | gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1, |
692 | gops->pmu.update_lspmu_cmdline_args = | ||
693 | gm20b_update_lspmu_cmdline_args; | ||
694 | gops->pmu.setup_apertures = gm20b_setup_apertures; | ||
692 | 695 | ||
693 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 696 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
694 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 697 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c index b245dbc6..33a36596 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.c | |||
@@ -237,20 +237,8 @@ static int bl_bootstrap(struct nvgpu_pmu *pmu, | |||
237 | return 0; | 237 | return 0; |
238 | } | 238 | } |
239 | 239 | ||
240 | int gv11b_init_pmu_setup_hw1(struct gk20a *g, | 240 | void gv11b_setup_apertures(struct gk20a *g) |
241 | void *desc, u32 bl_sz) | ||
242 | { | 241 | { |
243 | |||
244 | struct nvgpu_pmu *pmu = &g->pmu; | ||
245 | int err; | ||
246 | |||
247 | gk20a_dbg_fn(""); | ||
248 | |||
249 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
250 | nvgpu_flcn_reset(pmu->flcn); | ||
251 | pmu->isr_enabled = true; | ||
252 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
253 | |||
254 | /* setup apertures - virtual */ | 242 | /* setup apertures - virtual */ |
255 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | 243 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), |
256 | pwr_fbif_transcfg_mem_type_physical_f() | | 244 | pwr_fbif_transcfg_mem_type_physical_f() | |
@@ -267,19 +255,26 @@ int gv11b_init_pmu_setup_hw1(struct gk20a *g, | |||
267 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | 255 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), |
268 | pwr_fbif_transcfg_mem_type_physical_f() | | 256 | pwr_fbif_transcfg_mem_type_physical_f() | |
269 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | 257 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); |
258 | } | ||
259 | |||
260 | int gv11b_init_pmu_setup_hw1(struct gk20a *g, | ||
261 | void *desc, u32 bl_sz) | ||
262 | { | ||
263 | struct nvgpu_pmu *pmu = &g->pmu; | ||
264 | int err; | ||
265 | |||
266 | gk20a_dbg_fn(""); | ||
267 | |||
268 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
269 | nvgpu_flcn_reset(pmu->flcn); | ||
270 | pmu->isr_enabled = true; | ||
271 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
272 | |||
273 | if (g->ops.pmu.setup_apertures) | ||
274 | g->ops.pmu.setup_apertures(g); | ||
275 | if (g->ops.pmu.update_lspmu_cmdline_args) | ||
276 | g->ops.pmu.update_lspmu_cmdline_args(g); | ||
270 | 277 | ||
271 | /*Copying pmu cmdline args*/ | ||
272 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | ||
273 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); | ||
274 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
275 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
276 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
277 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
278 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
279 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
280 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
281 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
282 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
283 | /*disable irqs for hs falcon booting as we will poll for halt*/ | 278 | /*disable irqs for hs falcon booting as we will poll for halt*/ |
284 | nvgpu_mutex_acquire(&pmu->isr_mutex); | 279 | nvgpu_mutex_acquire(&pmu->isr_mutex); |
285 | pmu_enable_irq(pmu, false); | 280 | pmu_enable_irq(pmu, false); |
diff --git a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h index 72b3ec35..5fbe45e2 100644 --- a/drivers/gpu/nvgpu/gv11b/acr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/acr_gv11b.h | |||
@@ -27,4 +27,5 @@ | |||
27 | int gv11b_bootstrap_hs_flcn(struct gk20a *g); | 27 | int gv11b_bootstrap_hs_flcn(struct gk20a *g); |
28 | int gv11b_init_pmu_setup_hw1(struct gk20a *g, | 28 | int gv11b_init_pmu_setup_hw1(struct gk20a *g, |
29 | void *desc, u32 bl_sz); | 29 | void *desc, u32 bl_sz); |
30 | void gv11b_setup_apertures(struct gk20a *g); | ||
30 | #endif /*__PMU_GP106_H_*/ | 31 | #endif /*__PMU_GP106_H_*/ |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 8278d4e5..5649d758 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -747,6 +747,9 @@ int gv11b_init_hal(struct gk20a *g) | |||
747 | gops->pmu.falcon_clear_halt_interrupt_status = | 747 | gops->pmu.falcon_clear_halt_interrupt_status = |
748 | clear_halt_interrupt_status, | 748 | clear_halt_interrupt_status, |
749 | gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, | 749 | gops->pmu.init_falcon_setup_hw = gv11b_init_pmu_setup_hw1, |
750 | gops->pmu.update_lspmu_cmdline_args = | ||
751 | gm20b_update_lspmu_cmdline_args; | ||
752 | gops->pmu.setup_apertures = gv11b_setup_apertures; | ||
750 | 753 | ||
751 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | 754 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; |
752 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; | 755 | gops->pmu.load_lsfalcon_ucode = gp10b_load_falcon_ucode; |