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-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_channel.c21
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_channel.h11
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_dbg.c94
3 files changed, 113 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
index 3c844491..da35b93f 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics channel 2 * GK20A Graphics channel
3 * 3 *
4 * Copyright (c) 2011-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * This program is free software; you can redistribute it and/or modify it 6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 7 * under the terms and conditions of the GNU General Public License,
@@ -128,8 +128,7 @@ void gk20a_channel_free_cycle_stats_buffer(struct channel_gk20a *ch)
128 nvgpu_mutex_release(&ch->cyclestate.cyclestate_buffer_mutex); 128 nvgpu_mutex_release(&ch->cyclestate.cyclestate_buffer_mutex);
129} 129}
130 130
131static int gk20a_channel_cycle_stats(struct channel_gk20a *ch, 131int gk20a_channel_cycle_stats(struct channel_gk20a *ch, int dmabuf_fd)
132 struct nvgpu_cycle_stats_args *args)
133{ 132{
134 struct dma_buf *dmabuf; 133 struct dma_buf *dmabuf;
135 void *virtual_address; 134 void *virtual_address;
@@ -139,10 +138,10 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
139 if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS)) 138 if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS))
140 return -ENOSYS; 139 return -ENOSYS;
141 140
142 if (args->dmabuf_fd && !priv->cyclestate_buffer_handler) { 141 if (dmabuf_fd && !priv->cyclestate_buffer_handler) {
143 142
144 /* set up new cyclestats buffer */ 143 /* set up new cyclestats buffer */
145 dmabuf = dma_buf_get(args->dmabuf_fd); 144 dmabuf = dma_buf_get(dmabuf_fd);
146 if (IS_ERR(dmabuf)) 145 if (IS_ERR(dmabuf))
147 return PTR_ERR(dmabuf); 146 return PTR_ERR(dmabuf);
148 virtual_address = dma_buf_vmap(dmabuf); 147 virtual_address = dma_buf_vmap(dmabuf);
@@ -154,12 +153,12 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
154 ch->cyclestate.cyclestate_buffer_size = dmabuf->size; 153 ch->cyclestate.cyclestate_buffer_size = dmabuf->size;
155 return 0; 154 return 0;
156 155
157 } else if (!args->dmabuf_fd && priv->cyclestate_buffer_handler) { 156 } else if (!dmabuf_fd && priv->cyclestate_buffer_handler) {
158 gk20a_channel_free_cycle_stats_buffer(ch); 157 gk20a_channel_free_cycle_stats_buffer(ch);
159 return 0; 158 return 0;
160 159
161 } else if (!args->dmabuf_fd && !priv->cyclestate_buffer_handler) { 160 } else if (!dmabuf_fd && !priv->cyclestate_buffer_handler) {
162 /* no requst from GL */ 161 /* no request from GL */
163 return 0; 162 return 0;
164 163
165 } else { 164 } else {
@@ -168,7 +167,7 @@ static int gk20a_channel_cycle_stats(struct channel_gk20a *ch,
168 } 167 }
169} 168}
170 169
171static int gk20a_flush_cycle_stats_snapshot(struct channel_gk20a *ch) 170int gk20a_flush_cycle_stats_snapshot(struct channel_gk20a *ch)
172{ 171{
173 int ret; 172 int ret;
174 173
@@ -182,7 +181,7 @@ static int gk20a_flush_cycle_stats_snapshot(struct channel_gk20a *ch)
182 return ret; 181 return ret;
183} 182}
184 183
185static int gk20a_attach_cycle_stats_snapshot(struct channel_gk20a *ch, 184int gk20a_attach_cycle_stats_snapshot(struct channel_gk20a *ch,
186 u32 dmabuf_fd, 185 u32 dmabuf_fd,
187 u32 perfmon_id_count, 186 u32 perfmon_id_count,
188 u32 *perfmon_id_start) 187 u32 *perfmon_id_start)
@@ -1280,7 +1279,7 @@ long gk20a_channel_ioctl(struct file *filp,
1280 break; 1279 break;
1281 } 1280 }
1282 err = gk20a_channel_cycle_stats(ch, 1281 err = gk20a_channel_cycle_stats(ch,
1283 (struct nvgpu_cycle_stats_args *)buf); 1282 ((struct nvgpu_cycle_stats_args *)buf)->dmabuf_fd);
1284 gk20a_idle(ch->g); 1283 gk20a_idle(ch->g);
1285 break; 1284 break;
1286#endif 1285#endif
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_channel.h b/drivers/gpu/nvgpu/os/linux/ioctl_channel.h
index 48cff1ea..3e802899 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_channel.h
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_channel.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -36,9 +36,16 @@ long gk20a_channel_ioctl(struct file *filp,
36int gk20a_channel_open_ioctl(struct gk20a *g, 36int gk20a_channel_open_ioctl(struct gk20a *g,
37 struct nvgpu_channel_open_args *args); 37 struct nvgpu_channel_open_args *args);
38 38
39int gk20a_channel_free_cycle_stats_snapshot(struct channel_gk20a *ch); 39int gk20a_channel_cycle_stats(struct channel_gk20a *ch, int dmabuf_fd);
40void gk20a_channel_free_cycle_stats_buffer(struct channel_gk20a *ch); 40void gk20a_channel_free_cycle_stats_buffer(struct channel_gk20a *ch);
41 41
42int gk20a_attach_cycle_stats_snapshot(struct channel_gk20a *ch,
43 u32 dmabuf_fd,
44 u32 perfmon_id_count,
45 u32 *perfmon_id_start);
46int gk20a_flush_cycle_stats_snapshot(struct channel_gk20a *ch);
47int gk20a_channel_free_cycle_stats_snapshot(struct channel_gk20a *ch);
48
42extern const struct file_operations gk20a_channel_ops; 49extern const struct file_operations gk20a_channel_ops;
43 50
44u32 nvgpu_get_common_runlist_level(u32 level); 51u32 nvgpu_get_common_runlist_level(u32 level);
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index 0c9b10b5..b5a10717 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -42,6 +42,7 @@
42#include "os_linux.h" 42#include "os_linux.h"
43#include "platform_gk20a.h" 43#include "platform_gk20a.h"
44#include "ioctl_dbg.h" 44#include "ioctl_dbg.h"
45#include "ioctl_channel.h"
45#include "dmabuf_vidmem.h" 46#include "dmabuf_vidmem.h"
46 47
47struct dbg_session_gk20a_linux { 48struct dbg_session_gk20a_linux {
@@ -1935,6 +1936,87 @@ static int nvgpu_dbg_gpu_set_sm_exception_type_mask(
1935 return err; 1936 return err;
1936} 1937}
1937 1938
1939#if defined(CONFIG_GK20A_CYCLE_STATS)
1940static int nvgpu_dbg_gpu_cycle_stats(struct dbg_session_gk20a *dbg_s,
1941 struct nvgpu_dbg_gpu_cycle_stats_args *args)
1942{
1943 struct channel_gk20a *ch = NULL;
1944 int err;
1945
1946 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
1947 if (ch == NULL) {
1948 return -EINVAL;
1949 }
1950
1951 err = gk20a_busy(ch->g);
1952 if (err != 0) {
1953 return err;
1954 }
1955
1956 err = gk20a_channel_cycle_stats(ch, args->dmabuf_fd);
1957
1958 gk20a_idle(ch->g);
1959 return err;
1960}
1961
1962static int nvgpu_dbg_gpu_cycle_stats_snapshot(struct dbg_session_gk20a *dbg_s,
1963 struct nvgpu_dbg_gpu_cycle_stats_snapshot_args *args)
1964{
1965 struct channel_gk20a *ch = NULL;
1966 int err;
1967
1968 if (!args->dmabuf_fd) {
1969 return -EINVAL;
1970 }
1971
1972 nvgpu_speculation_barrier();
1973
1974 ch = nvgpu_dbg_gpu_get_session_channel(dbg_s);
1975 if (ch == NULL) {
1976 return -EINVAL;
1977 }
1978
1979 /* is it allowed to handle calls for current GPU? */
1980 if (!nvgpu_is_enabled(ch->g, NVGPU_SUPPORT_CYCLE_STATS_SNAPSHOT)) {
1981 return -ENOSYS;
1982 }
1983
1984 err = gk20a_busy(ch->g);
1985 if (err != 0) {
1986 return err;
1987 }
1988
1989 /* handle the command (most frequent cases first) */
1990 switch (args->cmd) {
1991 case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT_CMD_FLUSH:
1992 err = gk20a_flush_cycle_stats_snapshot(ch);
1993 args->extra = 0;
1994 break;
1995
1996 case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT_CMD_ATTACH:
1997 err = gk20a_attach_cycle_stats_snapshot(ch,
1998 args->dmabuf_fd,
1999 args->extra,
2000 &args->extra);
2001 break;
2002
2003 case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT_CMD_DETACH:
2004 err = gk20a_channel_free_cycle_stats_snapshot(ch);
2005 args->extra = 0;
2006 break;
2007
2008 default:
2009 pr_err("cyclestats: unknown command %u\n", args->cmd);
2010 err = -EINVAL;
2011 break;
2012 }
2013
2014 gk20a_idle(ch->g);
2015 return err;
2016}
2017
2018#endif
2019
1938int gk20a_dbg_gpu_dev_open(struct inode *inode, struct file *filp) 2020int gk20a_dbg_gpu_dev_open(struct inode *inode, struct file *filp)
1939{ 2021{
1940 struct nvgpu_os_linux *l = container_of(inode->i_cdev, 2022 struct nvgpu_os_linux *l = container_of(inode->i_cdev,
@@ -2096,6 +2178,18 @@ long gk20a_dbg_gpu_dev_ioctl(struct file *filp, unsigned int cmd,
2096 (struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf); 2178 (struct nvgpu_dbg_gpu_set_ctx_mmu_debug_mode_args *)buf);
2097 break; 2179 break;
2098 2180
2181#ifdef CONFIG_GK20A_CYCLE_STATS
2182 case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS:
2183 err = nvgpu_dbg_gpu_cycle_stats(dbg_s,
2184 (struct nvgpu_dbg_gpu_cycle_stats_args *)buf);
2185 break;
2186
2187 case NVGPU_DBG_GPU_IOCTL_CYCLE_STATS_SNAPSHOT:
2188 err = nvgpu_dbg_gpu_cycle_stats_snapshot(dbg_s,
2189 (struct nvgpu_dbg_gpu_cycle_stats_snapshot_args *)buf);
2190 break;
2191#endif
2192
2099 default: 2193 default:
2100 nvgpu_err(g, 2194 nvgpu_err(g,
2101 "unrecognized dbg gpu ioctl cmd: 0x%x", 2195 "unrecognized dbg gpu ioctl cmd: 0x%x",