diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 11 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | 12 |
8 files changed, 41 insertions, 52 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index f7515294..2a1fd03f 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -29,8 +29,8 @@ | |||
29 | #include <nvgpu/timers.h> | 29 | #include <nvgpu/timers.h> |
30 | #include <nvgpu/cond.h> | 30 | #include <nvgpu/cond.h> |
31 | #include <nvgpu/atomic.h> | 31 | #include <nvgpu/atomic.h> |
32 | #include <nvgpu/nvgpu_mem.h> | ||
32 | 33 | ||
33 | #include "gr_gk20a.h" | ||
34 | 34 | ||
35 | struct gk20a; | 35 | struct gk20a; |
36 | struct dbg_session_gk20a; | 36 | struct dbg_session_gk20a; |
@@ -266,7 +266,7 @@ struct channel_gk20a { | |||
266 | u64 virt_ctx; | 266 | u64 virt_ctx; |
267 | #endif | 267 | #endif |
268 | 268 | ||
269 | struct ctx_header_desc ctx_header; | 269 | struct nvgpu_mem ctx_header; |
270 | 270 | ||
271 | /* Any operating system specific data. */ | 271 | /* Any operating system specific data. */ |
272 | void *os_priv; | 272 | void *os_priv; |
diff --git a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c index b4a241e4..78b753d1 100644 --- a/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fecs_trace_gk20a.c | |||
@@ -669,7 +669,7 @@ int gk20a_fecs_trace_bind_channel(struct gk20a *g, | |||
669 | GK20A_FECS_TRACE_NUM_RECORDS)); | 669 | GK20A_FECS_TRACE_NUM_RECORDS)); |
670 | 670 | ||
671 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_VA)) | 671 | if (nvgpu_is_enabled(g, NVGPU_FECS_TRACE_VA)) |
672 | mem = &ch->ctx_header.mem; | 672 | mem = &ch->ctx_header; |
673 | 673 | ||
674 | nvgpu_mem_wr(g, mem, | 674 | nvgpu_mem_wr(g, mem, |
675 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), | 675 | ctxsw_prog_main_image_context_timestamp_buffer_ptr_o(), |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index dbf9ff05..ead5d34a 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -808,8 +808,7 @@ static int gr_gk20a_ctx_zcull_setup(struct gk20a *g, struct channel_gk20a *c) | |||
808 | struct tsg_gk20a *tsg; | 808 | struct tsg_gk20a *tsg; |
809 | struct nvgpu_gr_ctx *gr_ctx = NULL; | 809 | struct nvgpu_gr_ctx *gr_ctx = NULL; |
810 | struct nvgpu_mem *mem = NULL; | 810 | struct nvgpu_mem *mem = NULL; |
811 | struct ctx_header_desc *ctx = &c->ctx_header; | 811 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
812 | struct nvgpu_mem *ctxheader = &ctx->mem; | ||
813 | int ret = 0; | 812 | int ret = 0; |
814 | 813 | ||
815 | nvgpu_log_fn(g, " "); | 814 | nvgpu_log_fn(g, " "); |
@@ -1683,8 +1682,7 @@ int gr_gk20a_update_hwpm_ctxsw_mode(struct gk20a *g, | |||
1683 | struct pm_ctx_desc *pm_ctx; | 1682 | struct pm_ctx_desc *pm_ctx; |
1684 | u32 data; | 1683 | u32 data; |
1685 | u64 virt_addr = 0; | 1684 | u64 virt_addr = 0; |
1686 | struct ctx_header_desc *ctx = &c->ctx_header; | 1685 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
1687 | struct nvgpu_mem *ctxheader = &ctx->mem; | ||
1688 | int ret; | 1686 | int ret; |
1689 | 1687 | ||
1690 | nvgpu_log_fn(g, " "); | 1688 | nvgpu_log_fn(g, " "); |
@@ -6620,8 +6618,7 @@ static int gr_gk20a_ctx_patch_smpc(struct gk20a *g, | |||
6620 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | 6618 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); |
6621 | struct tsg_gk20a *tsg; | 6619 | struct tsg_gk20a *tsg; |
6622 | struct nvgpu_gr_ctx *gr_ctx; | 6620 | struct nvgpu_gr_ctx *gr_ctx; |
6623 | struct ctx_header_desc *ctx = &ch->ctx_header; | 6621 | struct nvgpu_mem *ctxheader = &ch->ctx_header; |
6624 | struct nvgpu_mem *ctxheader = &ctx->mem; | ||
6625 | 6622 | ||
6626 | tsg = tsg_gk20a_from_ch(ch); | 6623 | tsg = tsg_gk20a_from_ch(ch); |
6627 | if (!tsg) | 6624 | if (!tsg) |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index bd5e625d..0d32cca3 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -434,10 +434,6 @@ struct gr_gk20a { | |||
434 | 434 | ||
435 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); | 435 | void gk20a_fecs_dump_falcon_stats(struct gk20a *g); |
436 | 436 | ||
437 | struct ctx_header_desc { | ||
438 | struct nvgpu_mem mem; | ||
439 | }; | ||
440 | |||
441 | /* contexts associated with a TSG */ | 437 | /* contexts associated with a TSG */ |
442 | struct nvgpu_gr_ctx { | 438 | struct nvgpu_gr_ctx { |
443 | struct nvgpu_mem mem; | 439 | struct nvgpu_mem mem; |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index f5377bc3..0aa32f8a 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1183,8 +1183,7 @@ void gr_gp10b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1183 | { | 1183 | { |
1184 | struct tsg_gk20a *tsg; | 1184 | struct tsg_gk20a *tsg; |
1185 | struct nvgpu_gr_ctx *gr_ctx; | 1185 | struct nvgpu_gr_ctx *gr_ctx; |
1186 | struct ctx_header_desc *ctx = &c->ctx_header; | 1186 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
1187 | struct nvgpu_mem *ctxheader = &ctx->mem; | ||
1188 | u32 gfxp_preempt_option = | 1187 | u32 gfxp_preempt_option = |
1189 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); | 1188 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); |
1190 | u32 cilp_preempt_option = | 1189 | u32 cilp_preempt_option = |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 296d8e90..9a6afa3e 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1682,8 +1682,7 @@ void gr_gv11b_update_ctxsw_preemption_mode(struct gk20a *g, | |||
1682 | { | 1682 | { |
1683 | struct tsg_gk20a *tsg; | 1683 | struct tsg_gk20a *tsg; |
1684 | struct nvgpu_gr_ctx *gr_ctx; | 1684 | struct nvgpu_gr_ctx *gr_ctx; |
1685 | struct ctx_header_desc *ctx = &c->ctx_header; | 1685 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
1686 | struct nvgpu_mem *ctxheader = &ctx->mem; | ||
1687 | u32 gfxp_preempt_option = | 1686 | u32 gfxp_preempt_option = |
1688 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); | 1687 | ctxsw_prog_main_image_graphics_preemption_options_control_gfxp_f(); |
1689 | u32 cilp_preempt_option = | 1688 | u32 cilp_preempt_option = |
@@ -2897,7 +2896,7 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2897 | { | 2896 | { |
2898 | u32 addr_lo; | 2897 | u32 addr_lo; |
2899 | u32 addr_hi; | 2898 | u32 addr_hi; |
2900 | struct ctx_header_desc *ctx; | 2899 | struct nvgpu_mem *ctxheader; |
2901 | int err; | 2900 | int err; |
2902 | struct gk20a *g = c->g; | 2901 | struct gk20a *g = c->g; |
2903 | 2902 | ||
@@ -2913,9 +2912,9 @@ int gr_gv11b_commit_inst(struct channel_gk20a *c, u64 gpu_va) | |||
2913 | return err; | 2912 | return err; |
2914 | } | 2913 | } |
2915 | 2914 | ||
2916 | ctx = &c->ctx_header; | 2915 | ctxheader = &c->ctx_header; |
2917 | addr_lo = u64_lo32(ctx->mem.gpu_va) >> ram_in_base_shift_v(); | 2916 | addr_lo = u64_lo32(ctxheader->gpu_va) >> ram_in_base_shift_v(); |
2918 | addr_hi = u64_hi32(ctx->mem.gpu_va); | 2917 | addr_hi = u64_hi32(ctxheader->gpu_va); |
2919 | 2918 | ||
2920 | /* point this address to engine_wfi_ptr */ | 2919 | /* point this address to engine_wfi_ptr */ |
2921 | nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), | 2920 | nvgpu_mem_wr32(c->g, &c->inst_block, ram_in_engine_wfi_target_w(), |
diff --git a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c index d742e8dc..4e429567 100644 --- a/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/subctx_gv11b.c | |||
@@ -43,42 +43,42 @@ static void gv11b_subctx_commit_pdb(struct vm_gk20a *vm, | |||
43 | 43 | ||
44 | void gv11b_free_subctx_header(struct channel_gk20a *c) | 44 | void gv11b_free_subctx_header(struct channel_gk20a *c) |
45 | { | 45 | { |
46 | struct ctx_header_desc *ctx = &c->ctx_header; | 46 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
47 | struct gk20a *g = c->g; | 47 | struct gk20a *g = c->g; |
48 | 48 | ||
49 | nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); | 49 | nvgpu_log(g, gpu_dbg_fn, "gv11b_free_subctx_header"); |
50 | 50 | ||
51 | if (ctx->mem.gpu_va) { | 51 | if (ctxheader->gpu_va) { |
52 | nvgpu_gmmu_unmap(c->vm, &ctx->mem, ctx->mem.gpu_va); | 52 | nvgpu_gmmu_unmap(c->vm, ctxheader, ctxheader->gpu_va); |
53 | 53 | ||
54 | nvgpu_dma_free(g, &ctx->mem); | 54 | nvgpu_dma_free(g, ctxheader); |
55 | } | 55 | } |
56 | } | 56 | } |
57 | 57 | ||
58 | int gv11b_alloc_subctx_header(struct channel_gk20a *c) | 58 | int gv11b_alloc_subctx_header(struct channel_gk20a *c) |
59 | { | 59 | { |
60 | struct ctx_header_desc *ctx = &c->ctx_header; | 60 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
61 | struct gk20a *g = c->g; | 61 | struct gk20a *g = c->g; |
62 | int ret = 0; | 62 | int ret = 0; |
63 | 63 | ||
64 | nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); | 64 | nvgpu_log(g, gpu_dbg_fn, "gv11b_alloc_subctx_header"); |
65 | 65 | ||
66 | if (!nvgpu_mem_is_valid(&ctx->mem)) { | 66 | if (!nvgpu_mem_is_valid(ctxheader)) { |
67 | ret = nvgpu_dma_alloc_sys(g, ctxsw_prog_fecs_header_v(), | 67 | ret = nvgpu_dma_alloc_sys(g, ctxsw_prog_fecs_header_v(), |
68 | &ctx->mem); | 68 | ctxheader); |
69 | if (ret) { | 69 | if (ret) { |
70 | nvgpu_err(g, "failed to allocate sub ctx header"); | 70 | nvgpu_err(g, "failed to allocate sub ctx header"); |
71 | return ret; | 71 | return ret; |
72 | } | 72 | } |
73 | ctx->mem.gpu_va = nvgpu_gmmu_map(c->vm, | 73 | ctxheader->gpu_va = nvgpu_gmmu_map(c->vm, |
74 | &ctx->mem, | 74 | ctxheader, |
75 | ctx->mem.size, | 75 | ctxheader->size, |
76 | 0, /* not GPU-cacheable */ | 76 | 0, /* not GPU-cacheable */ |
77 | gk20a_mem_flag_none, true, | 77 | gk20a_mem_flag_none, true, |
78 | ctx->mem.aperture); | 78 | ctxheader->aperture); |
79 | if (!ctx->mem.gpu_va) { | 79 | if (!ctxheader->gpu_va) { |
80 | nvgpu_err(g, "failed to map ctx header"); | 80 | nvgpu_err(g, "failed to map ctx header"); |
81 | nvgpu_dma_free(g, &ctx->mem); | 81 | nvgpu_dma_free(g, ctxheader); |
82 | return -ENOMEM; | 82 | return -ENOMEM; |
83 | } | 83 | } |
84 | } | 84 | } |
@@ -96,8 +96,7 @@ void gv11b_init_subcontext_pdb(struct vm_gk20a *vm, | |||
96 | 96 | ||
97 | int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) | 97 | int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) |
98 | { | 98 | { |
99 | struct ctx_header_desc *ctx = &c->ctx_header; | 99 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
100 | struct nvgpu_mem *gr_mem; | ||
101 | struct gk20a *g = c->g; | 100 | struct gk20a *g = c->g; |
102 | int ret = 0; | 101 | int ret = 0; |
103 | u32 addr_lo, addr_hi; | 102 | u32 addr_lo, addr_hi; |
@@ -111,40 +110,39 @@ int gv11b_update_subctx_header(struct channel_gk20a *c, u64 gpu_va) | |||
111 | 110 | ||
112 | gr_ctx = &tsg->gr_ctx; | 111 | gr_ctx = &tsg->gr_ctx; |
113 | 112 | ||
114 | gr_mem = &ctx->mem; | ||
115 | g->ops.mm.l2_flush(g, true); | 113 | g->ops.mm.l2_flush(g, true); |
116 | 114 | ||
117 | /* set priv access map */ | 115 | /* set priv access map */ |
118 | addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); | 116 | addr_lo = u64_lo32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); |
119 | addr_hi = u64_hi32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); | 117 | addr_hi = u64_hi32(gr_ctx->global_ctx_buffer_va[PRIV_ACCESS_MAP_VA]); |
120 | nvgpu_mem_wr(g, gr_mem, | 118 | nvgpu_mem_wr(g, ctxheader, |
121 | ctxsw_prog_main_image_priv_access_map_addr_lo_o(), | 119 | ctxsw_prog_main_image_priv_access_map_addr_lo_o(), |
122 | addr_lo); | 120 | addr_lo); |
123 | nvgpu_mem_wr(g, gr_mem, | 121 | nvgpu_mem_wr(g, ctxheader, |
124 | ctxsw_prog_main_image_priv_access_map_addr_hi_o(), | 122 | ctxsw_prog_main_image_priv_access_map_addr_hi_o(), |
125 | addr_hi); | 123 | addr_hi); |
126 | 124 | ||
127 | addr_lo = u64_lo32(gr_ctx->patch_ctx.mem.gpu_va); | 125 | addr_lo = u64_lo32(gr_ctx->patch_ctx.mem.gpu_va); |
128 | addr_hi = u64_hi32(gr_ctx->patch_ctx.mem.gpu_va); | 126 | addr_hi = u64_hi32(gr_ctx->patch_ctx.mem.gpu_va); |
129 | nvgpu_mem_wr(g, gr_mem, | 127 | nvgpu_mem_wr(g, ctxheader, |
130 | ctxsw_prog_main_image_patch_adr_lo_o(), | 128 | ctxsw_prog_main_image_patch_adr_lo_o(), |
131 | addr_lo); | 129 | addr_lo); |
132 | nvgpu_mem_wr(g, gr_mem, | 130 | nvgpu_mem_wr(g, ctxheader, |
133 | ctxsw_prog_main_image_patch_adr_hi_o(), | 131 | ctxsw_prog_main_image_patch_adr_hi_o(), |
134 | addr_hi); | 132 | addr_hi); |
135 | 133 | ||
136 | g->ops.gr.write_pm_ptr(g, gr_mem, gr_ctx->pm_ctx.mem.gpu_va); | 134 | g->ops.gr.write_pm_ptr(g, ctxheader, gr_ctx->pm_ctx.mem.gpu_va); |
137 | g->ops.gr.write_zcull_ptr(g, gr_mem, gr_ctx->zcull_ctx.gpu_va); | 135 | g->ops.gr.write_zcull_ptr(g, ctxheader, gr_ctx->zcull_ctx.gpu_va); |
138 | 136 | ||
139 | addr_lo = u64_lo32(gpu_va); | 137 | addr_lo = u64_lo32(gpu_va); |
140 | addr_hi = u64_hi32(gpu_va); | 138 | addr_hi = u64_hi32(gpu_va); |
141 | 139 | ||
142 | nvgpu_mem_wr(g, gr_mem, | 140 | nvgpu_mem_wr(g, ctxheader, |
143 | ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); | 141 | ctxsw_prog_main_image_context_buffer_ptr_hi_o(), addr_hi); |
144 | nvgpu_mem_wr(g, gr_mem, | 142 | nvgpu_mem_wr(g, ctxheader, |
145 | ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); | 143 | ctxsw_prog_main_image_context_buffer_ptr_o(), addr_lo); |
146 | 144 | ||
147 | nvgpu_mem_wr(g, gr_mem, | 145 | nvgpu_mem_wr(g, ctxheader, |
148 | ctxsw_prog_main_image_ctl_o(), | 146 | ctxsw_prog_main_image_ctl_o(), |
149 | ctxsw_prog_main_image_ctl_type_per_veid_header_v()); | 147 | ctxsw_prog_main_image_ctl_type_per_veid_header_v()); |
150 | 148 | ||
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c index b536d15e..b5272ae1 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_subctx_gv11b.c | |||
@@ -29,7 +29,7 @@ | |||
29 | 29 | ||
30 | int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) | 30 | int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) |
31 | { | 31 | { |
32 | struct ctx_header_desc *ctx = &c->ctx_header; | 32 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
33 | struct tegra_vgpu_cmd_msg msg = {}; | 33 | struct tegra_vgpu_cmd_msg msg = {}; |
34 | struct tegra_vgpu_alloc_ctx_header_params *p = | 34 | struct tegra_vgpu_alloc_ctx_header_params *p = |
35 | &msg.params.alloc_ctx_header; | 35 | &msg.params.alloc_ctx_header; |
@@ -53,20 +53,20 @@ int vgpu_gv11b_alloc_subctx_header(struct channel_gk20a *c) | |||
53 | GMMU_PAGE_SIZE_KERNEL); | 53 | GMMU_PAGE_SIZE_KERNEL); |
54 | return err; | 54 | return err; |
55 | } | 55 | } |
56 | ctx->mem.gpu_va = p->ctx_header_va; | 56 | ctxheader->gpu_va = p->ctx_header_va; |
57 | 57 | ||
58 | return err; | 58 | return err; |
59 | } | 59 | } |
60 | 60 | ||
61 | void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) | 61 | void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) |
62 | { | 62 | { |
63 | struct ctx_header_desc *ctx = &c->ctx_header; | 63 | struct nvgpu_mem *ctxheader = &c->ctx_header; |
64 | struct tegra_vgpu_cmd_msg msg = {}; | 64 | struct tegra_vgpu_cmd_msg msg = {}; |
65 | struct tegra_vgpu_free_ctx_header_params *p = | 65 | struct tegra_vgpu_free_ctx_header_params *p = |
66 | &msg.params.free_ctx_header; | 66 | &msg.params.free_ctx_header; |
67 | int err; | 67 | int err; |
68 | 68 | ||
69 | if (ctx->mem.gpu_va) { | 69 | if (ctxheader->gpu_va) { |
70 | msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER; | 70 | msg.cmd = TEGRA_VGPU_CMD_FREE_CTX_HEADER; |
71 | msg.handle = vgpu_get_handle(c->g); | 71 | msg.handle = vgpu_get_handle(c->g); |
72 | p->ch_handle = c->virt_ctx; | 72 | p->ch_handle = c->virt_ctx; |
@@ -74,8 +74,8 @@ void vgpu_gv11b_free_subctx_header(struct channel_gk20a *c) | |||
74 | err = err ? err : msg.ret; | 74 | err = err ? err : msg.ret; |
75 | if (unlikely(err)) | 75 | if (unlikely(err)) |
76 | nvgpu_err(c->g, "free ctx_header failed err %d", err); | 76 | nvgpu_err(c->g, "free ctx_header failed err %d", err); |
77 | __nvgpu_vm_free_va(c->vm, ctx->mem.gpu_va, | 77 | __nvgpu_vm_free_va(c->vm, ctxheader->gpu_va, |
78 | GMMU_PAGE_SIZE_KERNEL); | 78 | GMMU_PAGE_SIZE_KERNEL); |
79 | ctx->mem.gpu_va = 0; | 79 | ctxheader->gpu_va = 0; |
80 | } | 80 | } |
81 | } | 81 | } |