diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 170 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | 48 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 128 |
4 files changed, 350 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index d36aa6ec..0c0b4261 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -368,6 +368,170 @@ static int gr_gv11b_handle_cbu_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
368 | 368 | ||
369 | } | 369 | } |
370 | 370 | ||
371 | static int gr_gv11b_handle_l1_data_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
372 | bool *post_event, struct channel_gk20a *fault_ch, | ||
373 | u32 *hww_global_esr) | ||
374 | { | ||
375 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
376 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
377 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
378 | u32 l1_data_ecc_status, l1_data_ecc_corrected_err_status = 0; | ||
379 | u32 l1_data_ecc_uncorrected_err_status = 0; | ||
380 | u32 l1_data_corrected_err_count_delta = 0; | ||
381 | u32 l1_data_uncorrected_err_count_delta = 0; | ||
382 | bool is_l1_data_ecc_corrected_total_err_overflow = 0; | ||
383 | bool is_l1_data_ecc_uncorrected_total_err_overflow = 0; | ||
384 | |||
385 | /* Check for L1 data ECC errors. */ | ||
386 | l1_data_ecc_status = gk20a_readl(g, | ||
387 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() + offset); | ||
388 | l1_data_ecc_corrected_err_status = l1_data_ecc_status & | ||
389 | (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m() | | ||
390 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m()); | ||
391 | l1_data_ecc_uncorrected_err_status = l1_data_ecc_status & | ||
392 | (gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m() | | ||
393 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m()); | ||
394 | |||
395 | if ((l1_data_ecc_corrected_err_status == 0) && (l1_data_ecc_uncorrected_err_status == 0)) | ||
396 | return 0; | ||
397 | |||
398 | l1_data_corrected_err_count_delta = | ||
399 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v( | ||
400 | gk20a_readl(g, | ||
401 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + | ||
402 | offset)); | ||
403 | l1_data_uncorrected_err_count_delta = | ||
404 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v( | ||
405 | gk20a_readl(g, | ||
406 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + | ||
407 | offset)); | ||
408 | is_l1_data_ecc_corrected_total_err_overflow = | ||
409 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(l1_data_ecc_status); | ||
410 | is_l1_data_ecc_uncorrected_total_err_overflow = | ||
411 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(l1_data_ecc_status); | ||
412 | |||
413 | if ((l1_data_corrected_err_count_delta > 0) || is_l1_data_ecc_corrected_total_err_overflow) { | ||
414 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
415 | "corrected error (SBE) detected in SM L1 data! err_mask [%08x] is_overf [%d]", | ||
416 | l1_data_ecc_corrected_err_status, is_l1_data_ecc_corrected_total_err_overflow); | ||
417 | |||
418 | /* HW uses 16-bits counter */ | ||
419 | l1_data_corrected_err_count_delta += | ||
420 | (is_l1_data_ecc_corrected_total_err_overflow << | ||
421 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s()); | ||
422 | g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count.counters[tpc] += | ||
423 | l1_data_corrected_err_count_delta; | ||
424 | gk20a_writel(g, | ||
425 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r() + offset, | ||
426 | 0); | ||
427 | } | ||
428 | if ((l1_data_uncorrected_err_count_delta > 0) || is_l1_data_ecc_uncorrected_total_err_overflow) { | ||
429 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
430 | "Uncorrected error (DBE) detected in SM L1 data! err_mask [%08x] is_overf [%d]", | ||
431 | l1_data_ecc_uncorrected_err_status, is_l1_data_ecc_uncorrected_total_err_overflow); | ||
432 | |||
433 | /* HW uses 16-bits counter */ | ||
434 | l1_data_uncorrected_err_count_delta += | ||
435 | (is_l1_data_ecc_uncorrected_total_err_overflow << | ||
436 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s()); | ||
437 | g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count.counters[tpc] += | ||
438 | l1_data_uncorrected_err_count_delta; | ||
439 | gk20a_writel(g, | ||
440 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r() + offset, | ||
441 | 0); | ||
442 | } | ||
443 | |||
444 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r() + offset, | ||
445 | gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f()); | ||
446 | |||
447 | return 0; | ||
448 | |||
449 | } | ||
450 | |||
451 | static int gr_gv11b_handle_icache_exception(struct gk20a *g, u32 gpc, u32 tpc, | ||
452 | bool *post_event, struct channel_gk20a *fault_ch, | ||
453 | u32 *hww_global_esr) | ||
454 | { | ||
455 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
456 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
457 | u32 offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
458 | u32 icache_ecc_status, icache_ecc_corrected_err_status = 0; | ||
459 | u32 icache_ecc_uncorrected_err_status = 0; | ||
460 | u32 icache_corrected_err_count_delta = 0; | ||
461 | u32 icache_uncorrected_err_count_delta = 0; | ||
462 | bool is_icache_ecc_corrected_total_err_overflow = 0; | ||
463 | bool is_icache_ecc_uncorrected_total_err_overflow = 0; | ||
464 | |||
465 | /* Check for L0 && L1 icache ECC errors. */ | ||
466 | icache_ecc_status = gk20a_readl(g, | ||
467 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_r() + offset); | ||
468 | icache_ecc_corrected_err_status = icache_ecc_status & | ||
469 | (gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m() | | ||
470 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m() | | ||
471 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m() | | ||
472 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m()); | ||
473 | icache_ecc_uncorrected_err_status = icache_ecc_status & | ||
474 | (gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m() | | ||
475 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m() | | ||
476 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m() | | ||
477 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m()); | ||
478 | |||
479 | if ((icache_ecc_corrected_err_status == 0) && (icache_ecc_uncorrected_err_status == 0)) | ||
480 | return 0; | ||
481 | |||
482 | icache_corrected_err_count_delta = | ||
483 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v( | ||
484 | gk20a_readl(g, | ||
485 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + | ||
486 | offset)); | ||
487 | icache_uncorrected_err_count_delta = | ||
488 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v( | ||
489 | gk20a_readl(g, | ||
490 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + | ||
491 | offset)); | ||
492 | is_icache_ecc_corrected_total_err_overflow = | ||
493 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(icache_ecc_status); | ||
494 | is_icache_ecc_uncorrected_total_err_overflow = | ||
495 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(icache_ecc_status); | ||
496 | |||
497 | if ((icache_corrected_err_count_delta > 0) || is_icache_ecc_corrected_total_err_overflow) { | ||
498 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
499 | "corrected error (SBE) detected in SM L0 && L1 icache! err_mask [%08x] is_overf [%d]", | ||
500 | icache_ecc_corrected_err_status, is_icache_ecc_corrected_total_err_overflow); | ||
501 | |||
502 | /* HW uses 16-bits counter */ | ||
503 | icache_corrected_err_count_delta += | ||
504 | (is_icache_ecc_corrected_total_err_overflow << | ||
505 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s()); | ||
506 | g->gr.t19x.ecc_stats.sm_icache_corrected_err_count.counters[tpc] += | ||
507 | icache_corrected_err_count_delta; | ||
508 | gk20a_writel(g, | ||
509 | gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r() + offset, | ||
510 | 0); | ||
511 | } | ||
512 | if ((icache_uncorrected_err_count_delta > 0) || is_icache_ecc_uncorrected_total_err_overflow) { | ||
513 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
514 | "Uncorrected error (DBE) detected in SM L0 && L1 icache! err_mask [%08x] is_overf [%d]", | ||
515 | icache_ecc_uncorrected_err_status, is_icache_ecc_uncorrected_total_err_overflow); | ||
516 | |||
517 | /* HW uses 16-bits counter */ | ||
518 | icache_uncorrected_err_count_delta += | ||
519 | (is_icache_ecc_uncorrected_total_err_overflow << | ||
520 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s()); | ||
521 | g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count.counters[tpc] += | ||
522 | icache_uncorrected_err_count_delta; | ||
523 | gk20a_writel(g, | ||
524 | gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r() + offset, | ||
525 | 0); | ||
526 | } | ||
527 | |||
528 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_icache_ecc_status_r() + offset, | ||
529 | gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f()); | ||
530 | |||
531 | return 0; | ||
532 | |||
533 | } | ||
534 | |||
371 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | 535 | static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, |
372 | bool *post_event, struct channel_gk20a *fault_ch, | 536 | bool *post_event, struct channel_gk20a *fault_ch, |
373 | u32 *hww_global_esr) | 537 | u32 *hww_global_esr) |
@@ -383,6 +547,12 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
383 | /* Check for CBU ECC errors. */ | 547 | /* Check for CBU ECC errors. */ |
384 | gr_gv11b_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | 548 | gr_gv11b_handle_cbu_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); |
385 | 549 | ||
550 | /* Check for L1 data ECC errors. */ | ||
551 | gr_gv11b_handle_l1_data_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | ||
552 | |||
553 | /* Check for L0 && L1 icache ECC errors. */ | ||
554 | gr_gv11b_handle_icache_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | ||
555 | |||
386 | return ret; | 556 | return ret; |
387 | } | 557 | } |
388 | 558 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index b350862c..5bcbe667 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -41,6 +41,10 @@ struct gr_t19x { | |||
41 | struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; | 41 | struct gr_gp10b_ecc_stat sm_l1_tag_uncorrected_err_count; |
42 | struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; | 42 | struct gr_gp10b_ecc_stat sm_cbu_corrected_err_count; |
43 | struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; | 43 | struct gr_gp10b_ecc_stat sm_cbu_uncorrected_err_count; |
44 | struct gr_gp10b_ecc_stat sm_l1_data_corrected_err_count; | ||
45 | struct gr_gp10b_ecc_stat sm_l1_data_uncorrected_err_count; | ||
46 | struct gr_gp10b_ecc_stat sm_icache_corrected_err_count; | ||
47 | struct gr_gp10b_ecc_stat sm_icache_uncorrected_err_count; | ||
44 | } ecc_stats; | 48 | } ecc_stats; |
45 | }; | 49 | }; |
46 | 50 | ||
diff --git a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c index d235b261..009e5716 100644 --- a/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c +++ b/drivers/gpu/nvgpu/gv11b/platform_gv11b_tegra.c | |||
@@ -127,6 +127,10 @@ static struct device_attribute *dev_attr_sm_l1_tag_ecc_corrected_err_count_array | |||
127 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; | 127 | static struct device_attribute *dev_attr_sm_l1_tag_ecc_uncorrected_err_count_array; |
128 | static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; | 128 | static struct device_attribute *dev_attr_sm_cbu_ecc_corrected_err_count_array; |
129 | static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; | 129 | static struct device_attribute *dev_attr_sm_cbu_ecc_uncorrected_err_count_array; |
130 | static struct device_attribute *dev_attr_sm_l1_data_ecc_corrected_err_count_array; | ||
131 | static struct device_attribute *dev_attr_sm_l1_data_ecc_uncorrected_err_count_array; | ||
132 | static struct device_attribute *dev_attr_sm_icache_ecc_corrected_err_count_array; | ||
133 | static struct device_attribute *dev_attr_sm_icache_ecc_uncorrected_err_count_array; | ||
130 | 134 | ||
131 | void gr_gv11b_create_sysfs(struct device *dev) | 135 | void gr_gv11b_create_sysfs(struct device *dev) |
132 | { | 136 | { |
@@ -165,6 +169,30 @@ void gr_gv11b_create_sysfs(struct device *dev) | |||
165 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, | 169 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, |
166 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 170 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
167 | 171 | ||
172 | error |= gr_gp10b_ecc_stat_create(dev, | ||
173 | 0, | ||
174 | "sm_l1_data_ecc_corrected_err_count", | ||
175 | &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, | ||
176 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); | ||
177 | |||
178 | error |= gr_gp10b_ecc_stat_create(dev, | ||
179 | 0, | ||
180 | "sm_l1_data_ecc_uncorrected_err_count", | ||
181 | &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, | ||
182 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | ||
183 | |||
184 | error |= gr_gp10b_ecc_stat_create(dev, | ||
185 | 0, | ||
186 | "sm_icache_ecc_corrected_err_count", | ||
187 | &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, | ||
188 | dev_attr_sm_icache_ecc_corrected_err_count_array); | ||
189 | |||
190 | error |= gr_gp10b_ecc_stat_create(dev, | ||
191 | 0, | ||
192 | "sm_icache_ecc_uncorrected_err_count", | ||
193 | &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, | ||
194 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); | ||
195 | |||
168 | if (error) | 196 | if (error) |
169 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); | 197 | dev_err(dev, "Failed to create gv11b sysfs attributes!\n"); |
170 | } | 198 | } |
@@ -193,4 +221,24 @@ static void gr_gv11b_remove_sysfs(struct device *dev) | |||
193 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, | 221 | &g->gr.t19x.ecc_stats.sm_cbu_uncorrected_err_count, |
194 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); | 222 | dev_attr_sm_cbu_ecc_uncorrected_err_count_array); |
195 | 223 | ||
224 | gr_gp10b_ecc_stat_remove(dev, | ||
225 | 0, | ||
226 | &g->gr.t19x.ecc_stats.sm_l1_data_corrected_err_count, | ||
227 | dev_attr_sm_l1_data_ecc_corrected_err_count_array); | ||
228 | |||
229 | gr_gp10b_ecc_stat_remove(dev, | ||
230 | 0, | ||
231 | &g->gr.t19x.ecc_stats.sm_l1_data_uncorrected_err_count, | ||
232 | dev_attr_sm_l1_data_ecc_uncorrected_err_count_array); | ||
233 | |||
234 | gr_gp10b_ecc_stat_remove(dev, | ||
235 | 0, | ||
236 | &g->gr.t19x.ecc_stats.sm_icache_corrected_err_count, | ||
237 | dev_attr_sm_icache_ecc_corrected_err_count_array); | ||
238 | |||
239 | gr_gp10b_ecc_stat_remove(dev, | ||
240 | 0, | ||
241 | &g->gr.t19x.ecc_stats.sm_icache_uncorrected_err_count, | ||
242 | dev_attr_sm_icache_ecc_uncorrected_err_count_array); | ||
243 | |||
196 | } | 244 | } |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index 4b2e8c32..4ce69743 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -582,6 +582,134 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_uncorrected_err_count_total_v(u32 | |||
582 | { | 582 | { |
583 | return (r >> 0) & 0xffff; | 583 | return (r >> 0) & 0xffff; |
584 | } | 584 | } |
585 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_r(void) | ||
586 | { | ||
587 | return 0x0050436c; | ||
588 | } | ||
589 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_0_m(void) | ||
590 | { | ||
591 | return 0x1 << 0; | ||
592 | } | ||
593 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_el1_1_m(void) | ||
594 | { | ||
595 | return 0x1 << 1; | ||
596 | } | ||
597 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_0_m(void) | ||
598 | { | ||
599 | return 0x1 << 2; | ||
600 | } | ||
601 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_el1_1_m(void) | ||
602 | { | ||
603 | return 0x1 << 3; | ||
604 | } | ||
605 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
606 | { | ||
607 | return (r >> 8) & 0x1; | ||
608 | } | ||
609 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
610 | { | ||
611 | return (r >> 10) & 0x1; | ||
612 | } | ||
613 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_status_reset_task_f(void) | ||
614 | { | ||
615 | return 0x40000000; | ||
616 | } | ||
617 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_r(void) | ||
618 | { | ||
619 | return 0x00504370; | ||
620 | } | ||
621 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_s(void) | ||
622 | { | ||
623 | return 16; | ||
624 | } | ||
625 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_corrected_err_count_total_v(u32 r) | ||
626 | { | ||
627 | return (r >> 0) & 0xffff; | ||
628 | } | ||
629 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_r(void) | ||
630 | { | ||
631 | return 0x00504374; | ||
632 | } | ||
633 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_s(void) | ||
634 | { | ||
635 | return 16; | ||
636 | } | ||
637 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_data_ecc_uncorrected_err_count_total_v(u32 r) | ||
638 | { | ||
639 | return (r >> 0) & 0xffff; | ||
640 | } | ||
641 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_r(void) | ||
642 | { | ||
643 | return 0x0050464c; | ||
644 | } | ||
645 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_data_m(void) | ||
646 | { | ||
647 | return 0x1 << 0; | ||
648 | } | ||
649 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l0_predecode_m(void) | ||
650 | { | ||
651 | return 0x1 << 1; | ||
652 | } | ||
653 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_data_m(void) | ||
654 | { | ||
655 | return 0x1 << 2; | ||
656 | } | ||
657 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_l1_predecode_m(void) | ||
658 | { | ||
659 | return 0x1 << 3; | ||
660 | } | ||
661 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_data_m(void) | ||
662 | { | ||
663 | return 0x1 << 4; | ||
664 | } | ||
665 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l0_predecode_m(void) | ||
666 | { | ||
667 | return 0x1 << 5; | ||
668 | } | ||
669 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_data_m(void) | ||
670 | { | ||
671 | return 0x1 << 6; | ||
672 | } | ||
673 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_l1_predecode_m(void) | ||
674 | { | ||
675 | return 0x1 << 7; | ||
676 | } | ||
677 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_corrected_err_total_counter_overflow_v(u32 r) | ||
678 | { | ||
679 | return (r >> 16) & 0x1; | ||
680 | } | ||
681 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_uncorrected_err_total_counter_overflow_v(u32 r) | ||
682 | { | ||
683 | return (r >> 18) & 0x1; | ||
684 | } | ||
685 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_status_reset_task_f(void) | ||
686 | { | ||
687 | return 0x40000000; | ||
688 | } | ||
689 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_r(void) | ||
690 | { | ||
691 | return 0x00504650; | ||
692 | } | ||
693 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_s(void) | ||
694 | { | ||
695 | return 16; | ||
696 | } | ||
697 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_corrected_err_count_total_v(u32 r) | ||
698 | { | ||
699 | return (r >> 0) & 0xffff; | ||
700 | } | ||
701 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_r(void) | ||
702 | { | ||
703 | return 0x00504654; | ||
704 | } | ||
705 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_s(void) | ||
706 | { | ||
707 | return 16; | ||
708 | } | ||
709 | static inline u32 gr_pri_gpc0_tpc0_sm_icache_ecc_uncorrected_err_count_total_v(u32 r) | ||
710 | { | ||
711 | return (r >> 0) & 0xffff; | ||
712 | } | ||
585 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) | 713 | static inline u32 gr_pri_gpc0_tpc0_sm_l1_tag_ecc_status_r(void) |
586 | { | 714 | { |
587 | return 0x00504624; | 715 | return 0x00504624; |