diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/ctrl/ctrlperf.h | 66 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/bios.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h | 45 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/vfe_var.c | 55 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/perf/vfe_var.h | 12 |
5 files changed, 119 insertions, 62 deletions
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlperf.h b/drivers/gpu/nvgpu/ctrl/ctrlperf.h index 52ff60c7..477b33d8 100644 --- a/drivers/gpu/nvgpu/ctrl/ctrlperf.h +++ b/drivers/gpu/nvgpu/ctrl/ctrlperf.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * general p state infrastructure | 2 | * general p state infrastructure |
3 | * | 3 | * |
4 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -36,4 +36,68 @@ struct ctrl_perf_volt_rail_list { | |||
36 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; | 36 | rails[CTRL_VOLT_VOLT_RAIL_MAX_RAILS]; |
37 | }; | 37 | }; |
38 | 38 | ||
39 | union ctrl_perf_vfe_var_single_sensed_fuse_value_data { | ||
40 | int signed_value; | ||
41 | u32 unsigned_value; | ||
42 | }; | ||
43 | |||
44 | struct ctrl_perf_vfe_var_single_sensed_fuse_value { | ||
45 | bool b_signed; | ||
46 | union ctrl_perf_vfe_var_single_sensed_fuse_value_data data; | ||
47 | }; | ||
48 | |||
49 | struct ctrl_bios_vfield_register_segment_super { | ||
50 | u8 low_bit; | ||
51 | u8 high_bit; | ||
52 | }; | ||
53 | |||
54 | struct ctrl_bios_vfield_register_segment_reg { | ||
55 | struct ctrl_bios_vfield_register_segment_super super; | ||
56 | u32 addr; | ||
57 | }; | ||
58 | |||
59 | struct ctrl_bios_vfield_register_segment_index_reg { | ||
60 | struct ctrl_bios_vfield_register_segment_super super; | ||
61 | u32 addr; | ||
62 | u32 reg_index; | ||
63 | u32 index; | ||
64 | }; | ||
65 | |||
66 | union ctrl_bios_vfield_register_segment_data { | ||
67 | struct ctrl_bios_vfield_register_segment_reg reg; | ||
68 | struct ctrl_bios_vfield_register_segment_index_reg index_reg; | ||
69 | }; | ||
70 | |||
71 | struct ctrl_bios_vfield_register_segment { | ||
72 | u8 type; | ||
73 | union ctrl_bios_vfield_register_segment_data data; | ||
74 | }; | ||
75 | |||
76 | #define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 | ||
77 | |||
78 | struct ctrl_perf_vfe_var_single_sensed_fuse_info { | ||
79 | u8 segment_count; | ||
80 | struct ctrl_bios_vfield_register_segment segments[NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; | ||
81 | }; | ||
82 | |||
83 | struct ctrl_perf_vfe_var_single_sensed_fuse_override_info { | ||
84 | u32 fuse_val_override; | ||
85 | u8 b_fuse_regkey_override; | ||
86 | }; | ||
87 | |||
88 | struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info { | ||
89 | struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; | ||
90 | u32 fuse_val_default; | ||
91 | u32 hw_correction_scale; | ||
92 | int hw_correction_offset; | ||
93 | u8 v_field_id; | ||
94 | }; | ||
95 | |||
96 | struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info { | ||
97 | struct ctrl_perf_vfe_var_single_sensed_fuse_info fuse; | ||
98 | u8 ver_expected; | ||
99 | bool b_ver_check; | ||
100 | bool b_use_default_on_ver_check_fail; | ||
101 | u8 v_field_id_ver; | ||
102 | }; | ||
39 | #endif | 103 | #endif |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h index 191f0dbd..eec057f2 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/bios.h +++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h | |||
@@ -321,6 +321,9 @@ struct vbios_vfe_3x_var_entry_struct { | |||
321 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 | 321 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_MASK 0x1000000 |
322 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 | 322 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_SHIFT 24 |
323 | 323 | ||
324 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_MASK 0x2000000 | ||
325 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER_SHIFT 25 | ||
326 | |||
324 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 | 327 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES 0x00000001 |
325 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 | 328 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_NO 0x00000000 |
326 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF | 329 | #define VBIOS_VFE_3X_VAR_ENTRY_PAR0_DPROD_VFE_VAR_IDX_0_MASK 0xFF |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h index 18568a4d..7764c72a 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h +++ b/drivers/gpu/nvgpu/include/nvgpu/pmuif/gpmuifperfvfe.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -24,11 +24,11 @@ | |||
24 | 24 | ||
25 | #include "gpmuifbios.h" | 25 | #include "gpmuifbios.h" |
26 | #include "gpmuifboardobj.h" | 26 | #include "gpmuifboardobj.h" |
27 | #include "ctrl/ctrlperf.h" | ||
27 | 28 | ||
28 | #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 | 29 | #define CTRL_PERF_VFE_EQU_QUADRATIC_COEFF_COUNT 0x03 |
29 | #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 | 30 | #define NV_PMU_PERF_RPC_VFE_EQU_EVAL_VAR_COUNT_MAX 2 |
30 | #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 | 31 | #define NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX 16 |
31 | #define NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX 1 | ||
32 | 32 | ||
33 | struct nv_pmu_perf_vfe_var_value { | 33 | struct nv_pmu_perf_vfe_var_value { |
34 | u8 var_type; | 34 | u8 var_type; |
@@ -66,8 +66,8 @@ struct nv_pmu_perf_vfe_var_get_status_super { | |||
66 | 66 | ||
67 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { | 67 | struct nv_pmu_perf_vfe_var_single_sensed_fuse_get_status { |
68 | struct nv_pmu_perf_vfe_var_get_status_super super; | 68 | struct nv_pmu_perf_vfe_var_get_status_super super; |
69 | u32 fuse_value_integer; | 69 | struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_integer; |
70 | u32 fuse_value_hw_integer; | 70 | struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_value_hw_integer; |
71 | u8 fuse_version; | 71 | u8 fuse_version; |
72 | bool b_version_check_failed; | 72 | bool b_version_check_failed; |
73 | }; | 73 | }; |
@@ -84,6 +84,8 @@ struct nv_pmu_vfe_var { | |||
84 | struct nv_pmu_boardobj super; | 84 | struct nv_pmu_boardobj super; |
85 | u32 out_range_min; | 85 | u32 out_range_min; |
86 | u32 out_range_max; | 86 | u32 out_range_max; |
87 | struct ctrl_boardobjgrp_mask_e32 mask_dependent_vars; | ||
88 | struct ctrl_boardobjgrp_mask_e255 mask_dependent_equs; | ||
87 | }; | 89 | }; |
88 | 90 | ||
89 | struct nv_pmu_vfe_var_derived { | 91 | struct nv_pmu_vfe_var_derived { |
@@ -116,38 +118,13 @@ struct nv_pmu_vfe_var_single_sensed { | |||
116 | struct nv_pmu_vfe_var_single super; | 118 | struct nv_pmu_vfe_var_single super; |
117 | }; | 119 | }; |
118 | 120 | ||
119 | struct nv_pmu_vfe_var_single_sensed_fuse_info { | ||
120 | u8 segment_count; | ||
121 | union nv_pmu_bios_vfield_register_segment segments[ | ||
122 | NV_PMU_VFE_VAR_SINGLE_SENSED_FUSE_SEGMENTS_MAX]; | ||
123 | }; | ||
124 | |||
125 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info { | ||
126 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
127 | u32 fuse_val_default; | ||
128 | int hw_correction_scale; | ||
129 | int hw_correction_offset; | ||
130 | u8 v_field_id; | ||
131 | }; | ||
132 | |||
133 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info { | ||
134 | struct nv_pmu_vfe_var_single_sensed_fuse_info fuse; | ||
135 | u8 ver_expected; | ||
136 | bool b_ver_check; | ||
137 | bool b_use_default_on_ver_check_fail; | ||
138 | u8 v_field_id_ver; | ||
139 | }; | ||
140 | |||
141 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info { | ||
142 | u32 fuse_val_override; | ||
143 | bool b_fuse_regkey_override; | ||
144 | }; | ||
145 | |||
146 | struct nv_pmu_vfe_var_single_sensed_fuse { | 121 | struct nv_pmu_vfe_var_single_sensed_fuse { |
147 | struct nv_pmu_vfe_var_single_sensed super; | 122 | struct nv_pmu_vfe_var_single_sensed super; |
148 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; | 123 | struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info; |
149 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; | 124 | struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info; |
150 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; | 125 | struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; |
126 | struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default; | ||
127 | bool b_fuse_value_signed; | ||
151 | }; | 128 | }; |
152 | 129 | ||
153 | struct nv_pmu_vfe_var_single_sensed_temp { | 130 | struct nv_pmu_vfe_var_single_sensed_temp { |
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c index c46747c9..a44c39ad 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.c +++ b/drivers/gpu/nvgpu/perf/vfe_var.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -29,6 +29,7 @@ | |||
29 | #include "boardobj/boardobjgrp_e32.h" | 29 | #include "boardobj/boardobjgrp_e32.h" |
30 | #include "ctrl/ctrlclk.h" | 30 | #include "ctrl/ctrlclk.h" |
31 | #include "ctrl/ctrlvolt.h" | 31 | #include "ctrl/ctrlvolt.h" |
32 | #include "ctrl/ctrlperf.h" | ||
32 | 33 | ||
33 | static u32 devinit_get_vfe_var_table(struct gk20a *g, | 34 | static u32 devinit_get_vfe_var_table(struct gk20a *g, |
34 | struct vfe_vars *pvarobjs); | 35 | struct vfe_vars *pvarobjs); |
@@ -183,7 +184,7 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, | |||
183 | struct vfield_reg_entry vregentry; | 184 | struct vfield_reg_entry vregentry; |
184 | struct vfield_header vheader; | 185 | struct vfield_header vheader; |
185 | struct vfield_entry ventry; | 186 | struct vfield_entry ventry; |
186 | union nv_pmu_bios_vfield_register_segment *psegment = NULL; | 187 | struct ctrl_bios_vfield_register_segment *psegment = NULL; |
187 | u8 *psegmentcount = NULL; | 188 | u8 *psegmentcount = NULL; |
188 | u32 status = 0; | 189 | u32 status = 0; |
189 | 190 | ||
@@ -254,32 +255,34 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, | |||
254 | continue; | 255 | continue; |
255 | } | 256 | } |
256 | 257 | ||
257 | psegment->super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); | ||
258 | psegment->super.low_bit = (u8)(VFIELD_BIT_START(ventry)); | ||
259 | switch (VFIELD_CODE((&vregentry))) { | 258 | switch (VFIELD_CODE((&vregentry))) { |
260 | case NV_VFIELD_DESC_CODE_REG: | 259 | case NV_VFIELD_DESC_CODE_REG: |
261 | psegment->reg.super.type = | 260 | psegment->type = |
262 | NV_PMU_BIOS_VFIELD_DESC_CODE_REG; | 261 | NV_PMU_BIOS_VFIELD_DESC_CODE_REG; |
263 | psegment->reg.addr = vregentry.reg; | 262 | psegment->data.reg.addr = vregentry.reg; |
263 | psegment->data.reg.super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); | ||
264 | psegment->data.reg.super.low_bit = (u8)(VFIELD_BIT_START(ventry)); | ||
264 | break; | 265 | break; |
265 | 266 | ||
266 | case NV_VFIELD_DESC_CODE_INDEX_REG: | 267 | case NV_VFIELD_DESC_CODE_INDEX_REG: |
267 | psegment->index_reg.super.type = | 268 | psegment->type = |
268 | NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG; | 269 | NV_PMU_BIOS_VFIELD_DESC_CODE_INDEX_REG; |
269 | psegment->index_reg.addr = vregentry.reg; | 270 | psegment->data.index_reg.addr = vregentry.reg; |
270 | psegment->index_reg.index = vregentry.index; | 271 | psegment->data.index_reg.index = vregentry.index; |
271 | psegment->index_reg.reg_index = vregentry.reg_index; | 272 | psegment->data.index_reg.reg_index = vregentry.reg_index; |
273 | psegment->data.index_reg.super.high_bit = (u8)(VFIELD_BIT_STOP(ventry)); | ||
274 | psegment->data.index_reg.super.low_bit = (u8)(VFIELD_BIT_START(ventry)); | ||
272 | break; | 275 | break; |
273 | 276 | ||
274 | default: | 277 | default: |
275 | psegment->super.type = | 278 | psegment->type = |
276 | NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; | 279 | NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; |
277 | status = -EINVAL; | 280 | status = -EINVAL; |
278 | goto done; | 281 | goto done; |
279 | } | 282 | } |
280 | 283 | ||
281 | if (VFIELD_SIZE((&vregentry)) != NV_VFIELD_DESC_SIZE_DWORD) { | 284 | if (VFIELD_SIZE((&vregentry)) != NV_VFIELD_DESC_SIZE_DWORD) { |
282 | psegment->super.type = | 285 | psegment->type = |
283 | NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; | 286 | NV_PMU_BIOS_VFIELD_DESC_CODE_INVALID; |
284 | return -EINVAL; | 287 | return -EINVAL; |
285 | } | 288 | } |
@@ -287,7 +290,6 @@ static u32 dev_init_get_vfield_info(struct gk20a *g, | |||
287 | } | 290 | } |
288 | 291 | ||
289 | done: | 292 | done: |
290 | |||
291 | return status; | 293 | return status; |
292 | } | 294 | } |
293 | 295 | ||
@@ -310,7 +312,12 @@ static u32 _vfe_var_pmudatainit_super(struct gk20a *g, | |||
310 | 312 | ||
311 | pset->out_range_min = pvfe_var->out_range_min; | 313 | pset->out_range_min = pvfe_var->out_range_min; |
312 | pset->out_range_max = pvfe_var->out_range_max; | 314 | pset->out_range_max = pvfe_var->out_range_max; |
313 | 315 | status = boardobjgrpmask_export(&pvfe_var->mask_dependent_vars.super, | |
316 | pvfe_var->mask_dependent_vars.super.bitcount, | ||
317 | &pset->mask_dependent_vars.super); | ||
318 | status = boardobjgrpmask_export(&pvfe_var->mask_dependent_equs.super, | ||
319 | pvfe_var->mask_dependent_equs.super.bitcount, | ||
320 | &pset->mask_dependent_equs.super); | ||
314 | return status; | 321 | return status; |
315 | } | 322 | } |
316 | 323 | ||
@@ -336,7 +343,8 @@ static u32 vfe_var_construct_super(struct gk20a *g, | |||
336 | pvfevar->out_range_min = ptmpvar->out_range_min; | 343 | pvfevar->out_range_min = ptmpvar->out_range_min; |
337 | pvfevar->out_range_max = ptmpvar->out_range_max; | 344 | pvfevar->out_range_max = ptmpvar->out_range_max; |
338 | pvfevar->b_is_dynamic_valid = false; | 345 | pvfevar->b_is_dynamic_valid = false; |
339 | 346 | status = boardobjgrpmask_e32_init(&pvfevar->mask_dependent_vars, NULL); | |
347 | status = boardobjgrpmask_e255_init(&pvfevar->mask_dependent_equs, NULL); | ||
340 | gk20a_dbg_info(""); | 348 | gk20a_dbg_info(""); |
341 | 349 | ||
342 | return status; | 350 | return status; |
@@ -583,16 +591,17 @@ static u32 _vfe_var_pmudatainit_single_sensed_fuse(struct gk20a *g, | |||
583 | ppmudata; | 591 | ppmudata; |
584 | 592 | ||
585 | memcpy(&pset->vfield_info, &pvfe_var_single_sensed_fuse->vfield_info, | 593 | memcpy(&pset->vfield_info, &pvfe_var_single_sensed_fuse->vfield_info, |
586 | sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info)); | 594 | sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info)); |
587 | 595 | ||
588 | memcpy(&pset->vfield_ver_info, | 596 | memcpy(&pset->vfield_ver_info, |
589 | &pvfe_var_single_sensed_fuse->vfield_ver_info, | 597 | &pvfe_var_single_sensed_fuse->vfield_ver_info, |
590 | sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info)); | 598 | sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info)); |
591 | 599 | ||
592 | memcpy(&pset->override_info, | 600 | memcpy(&pset->override_info, |
593 | &pvfe_var_single_sensed_fuse->override_info, | 601 | &pvfe_var_single_sensed_fuse->override_info, |
594 | sizeof(struct nv_pmu_vfe_var_single_sensed_fuse_override_info)); | 602 | sizeof(struct ctrl_perf_vfe_var_single_sensed_fuse_override_info)); |
595 | 603 | ||
604 | pset->b_fuse_value_signed = pvfe_var_single_sensed_fuse->b_fuse_value_signed; | ||
596 | return status; | 605 | return status; |
597 | } | 606 | } |
598 | 607 | ||
@@ -661,7 +670,8 @@ static u32 vfe_var_construct_single_sensed_fuse(struct gk20a *g, | |||
661 | pvfevar->vfield_ver_info.b_use_default_on_ver_check_fail = | 670 | pvfevar->vfield_ver_info.b_use_default_on_ver_check_fail = |
662 | ptmpvar->vfield_ver_info.b_use_default_on_ver_check_fail; | 671 | ptmpvar->vfield_ver_info.b_use_default_on_ver_check_fail; |
663 | pvfevar->b_version_check_done = false; | 672 | pvfevar->b_version_check_done = false; |
664 | 673 | pvfevar->b_fuse_value_signed = | |
674 | ptmpvar->b_fuse_value_signed; | ||
665 | pvfevar->super.super.super.b_is_dynamic = false; | 675 | pvfevar->super.super.super.b_is_dynamic = false; |
666 | pvfevar->super.super.super.b_is_dynamic_valid = true; | 676 | pvfevar->super.super.super.b_is_dynamic_valid = true; |
667 | 677 | ||
@@ -899,7 +909,6 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, | |||
899 | /* Read table entries*/ | 909 | /* Read table entries*/ |
900 | vfevars_tbl_entry_ptr = vfevars_tbl_ptr + | 910 | vfevars_tbl_entry_ptr = vfevars_tbl_ptr + |
901 | vfevars_tbl_header.header_size; | 911 | vfevars_tbl_header.header_size; |
902 | |||
903 | for (index = 0; | 912 | for (index = 0; |
904 | index < vfevars_tbl_header.vfe_var_entry_count; | 913 | index < vfevars_tbl_header.vfe_var_entry_count; |
905 | index++) { | 914 | index++) { |
@@ -910,9 +919,6 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, | |||
910 | var_data.super.out_range_min = var.out_range_min; | 919 | var_data.super.out_range_min = var.out_range_min; |
911 | var_data.super.out_range_max = var.out_range_max; | 920 | var_data.super.out_range_max = var.out_range_max; |
912 | 921 | ||
913 | var_data.super.out_range_min = var.out_range_min; | ||
914 | var_data.super.out_range_max = var.out_range_max; | ||
915 | |||
916 | switch ((u8)var.type) { | 922 | switch ((u8)var.type) { |
917 | case VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED: | 923 | case VBIOS_VFE_3X_VAR_ENTRY_TYPE_DISABLED: |
918 | continue; | 924 | continue; |
@@ -955,6 +961,9 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g, | |||
955 | (BIOS_GET_FIELD(var.param0, | 961 | (BIOS_GET_FIELD(var.param0, |
956 | VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL) && | 962 | VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL) && |
957 | VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES); | 963 | VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_USE_DEFAULT_ON_VER_CHECK_FAIL_YES); |
964 | var_data.single_sensed_fuse.b_fuse_value_signed = | ||
965 | (u8)BIOS_GET_FIELD(var.param0, | ||
966 | VBIOS_VFE_3X_VAR_ENTRY_PAR0_SSFUSE_VALUE_SIGNED_INTEGER); | ||
958 | var_data.single_sensed_fuse.vfield_info.fuse_val_default = | 967 | var_data.single_sensed_fuse.vfield_info.fuse_val_default = |
959 | var.param1; | 968 | var.param1; |
960 | if (szfmt >= VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) { | 969 | if (szfmt >= VBIOS_VFE_3X_VAR_ENTRY_SIZE_19) { |
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.h b/drivers/gpu/nvgpu/perf/vfe_var.h index c443bc4b..3364f994 100644 --- a/drivers/gpu/nvgpu/perf/vfe_var.h +++ b/drivers/gpu/nvgpu/perf/vfe_var.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2016-2018, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -40,6 +40,8 @@ struct vfe_var { | |||
40 | struct boardobj super; | 40 | struct boardobj super; |
41 | u32 out_range_min; | 41 | u32 out_range_min; |
42 | u32 out_range_max; | 42 | u32 out_range_max; |
43 | struct boardobjgrpmask_e32 mask_dependent_vars; | ||
44 | struct boardobjgrpmask_e255 mask_dependent_equs; | ||
43 | bool b_is_dynamic_valid; | 45 | bool b_is_dynamic_valid; |
44 | bool b_is_dynamic; | 46 | bool b_is_dynamic; |
45 | }; | 47 | }; |
@@ -85,9 +87,11 @@ struct vfe_var_single_sensed { | |||
85 | 87 | ||
86 | struct vfe_var_single_sensed_fuse { | 88 | struct vfe_var_single_sensed_fuse { |
87 | struct vfe_var_single_sensed super; | 89 | struct vfe_var_single_sensed super; |
88 | struct nv_pmu_vfe_var_single_sensed_fuse_override_info override_info; | 90 | struct ctrl_perf_vfe_var_single_sensed_fuse_override_info override_info; |
89 | struct nv_pmu_vfe_var_single_sensed_fuse_vfield_info vfield_info; | 91 | struct ctrl_perf_vfe_var_single_sensed_fuse_vfield_info vfield_info; |
90 | struct nv_pmu_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; | 92 | struct ctrl_perf_vfe_var_single_sensed_fuse_ver_vfield_info vfield_ver_info; |
93 | struct ctrl_perf_vfe_var_single_sensed_fuse_value fuse_val_default; | ||
94 | bool b_fuse_value_signed; | ||
91 | u32 fuse_value_integer; | 95 | u32 fuse_value_integer; |
92 | u32 fuse_value_hw_integer; | 96 | u32 fuse_value_hw_integer; |
93 | u8 fuse_version; | 97 | u8 fuse_version; |