diff options
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/clk/clk_arb.c | 128 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c | 144 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | 43 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/clk_arb.h | 10 |
4 files changed, 172 insertions, 153 deletions
diff --git a/drivers/gpu/nvgpu/clk/clk_arb.c b/drivers/gpu/nvgpu/clk/clk_arb.c index eaf9d8a5..8b499b16 100644 --- a/drivers/gpu/nvgpu/clk/clk_arb.c +++ b/drivers/gpu/nvgpu/clk/clk_arb.c | |||
@@ -1525,3 +1525,131 @@ void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock) | |||
1525 | else | 1525 | else |
1526 | nvgpu_mutex_release(&arb->pstate_lock); | 1526 | nvgpu_mutex_release(&arb->pstate_lock); |
1527 | } | 1527 | } |
1528 | |||
1529 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | ||
1530 | { | ||
1531 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
1532 | |||
1533 | switch (api_domain) { | ||
1534 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1535 | return (clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0; | ||
1536 | |||
1537 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1538 | return (clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0; | ||
1539 | |||
1540 | default: | ||
1541 | return false; | ||
1542 | } | ||
1543 | } | ||
1544 | |||
1545 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
1546 | u16 *min_mhz, u16 *max_mhz) | ||
1547 | { | ||
1548 | int ret; | ||
1549 | |||
1550 | switch (api_domain) { | ||
1551 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1552 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1553 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | ||
1554 | return ret; | ||
1555 | |||
1556 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1557 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
1558 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); | ||
1559 | if (!ret) { | ||
1560 | *min_mhz /= 2; | ||
1561 | *max_mhz /= 2; | ||
1562 | } | ||
1563 | return ret; | ||
1564 | |||
1565 | default: | ||
1566 | return -EINVAL; | ||
1567 | } | ||
1568 | } | ||
1569 | |||
1570 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | ||
1571 | u32 api_domain, u32 *max_points, u16 *fpoints) | ||
1572 | { | ||
1573 | int err; | ||
1574 | u32 i; | ||
1575 | |||
1576 | switch (api_domain) { | ||
1577 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1578 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | ||
1579 | max_points, fpoints); | ||
1580 | if (err || !fpoints) | ||
1581 | return err; | ||
1582 | for (i = 0; i < *max_points; i++) | ||
1583 | fpoints[i] /= 2; | ||
1584 | return 0; | ||
1585 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1586 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | ||
1587 | max_points, fpoints); | ||
1588 | default: | ||
1589 | return -EINVAL; | ||
1590 | } | ||
1591 | } | ||
1592 | |||
1593 | int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | ||
1594 | u32 api_domain, u16 *freq_mhz) | ||
1595 | { | ||
1596 | int err = 0; | ||
1597 | struct nvgpu_clk_arb_target *target = session->target; | ||
1598 | |||
1599 | switch (api_domain) { | ||
1600 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1601 | *freq_mhz = target->mclk; | ||
1602 | break; | ||
1603 | |||
1604 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1605 | *freq_mhz = target->gpc2clk / 2ULL; | ||
1606 | break; | ||
1607 | |||
1608 | default: | ||
1609 | *freq_mhz = 0; | ||
1610 | err = -EINVAL; | ||
1611 | } | ||
1612 | return err; | ||
1613 | } | ||
1614 | |||
1615 | int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | ||
1616 | u32 api_domain, u16 *freq_mhz) | ||
1617 | { | ||
1618 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
1619 | int err = 0; | ||
1620 | struct nvgpu_clk_arb_target *actual = arb->actual; | ||
1621 | |||
1622 | switch (api_domain) { | ||
1623 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1624 | *freq_mhz = actual->mclk; | ||
1625 | break; | ||
1626 | |||
1627 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1628 | *freq_mhz = actual->gpc2clk / 2ULL; | ||
1629 | break; | ||
1630 | |||
1631 | default: | ||
1632 | *freq_mhz = 0; | ||
1633 | err = -EINVAL; | ||
1634 | } | ||
1635 | return err; | ||
1636 | } | ||
1637 | |||
1638 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | ||
1639 | u32 api_domain, u16 *freq_mhz) | ||
1640 | { | ||
1641 | switch (api_domain) { | ||
1642 | case NVGPU_CLK_DOMAIN_MCLK: | ||
1643 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / | ||
1644 | 1000000ULL; | ||
1645 | return 0; | ||
1646 | |||
1647 | case NVGPU_CLK_DOMAIN_GPCCLK: | ||
1648 | *freq_mhz = g->ops.clk.measure_freq(g, | ||
1649 | CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL; | ||
1650 | return 0; | ||
1651 | |||
1652 | default: | ||
1653 | return -EINVAL; | ||
1654 | } | ||
1655 | } | ||
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c index 9593e2b7..09d47722 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_clk_arb.c | |||
@@ -457,11 +457,11 @@ int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session, | |||
457 | } | 457 | } |
458 | 458 | ||
459 | switch (api_domain) { | 459 | switch (api_domain) { |
460 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | 460 | case NVGPU_CLK_DOMAIN_MCLK: |
461 | dev->mclk_target_mhz = target_mhz; | 461 | dev->mclk_target_mhz = target_mhz; |
462 | break; | 462 | break; |
463 | 463 | ||
464 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | 464 | case NVGPU_CLK_DOMAIN_GPCCLK: |
465 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; | 465 | dev->gpc2clk_target_mhz = target_mhz * 2ULL; |
466 | break; | 466 | break; |
467 | 467 | ||
@@ -474,107 +474,6 @@ fdput_fd: | |||
474 | return err; | 474 | return err; |
475 | } | 475 | } |
476 | 476 | ||
477 | int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session, | ||
478 | u32 api_domain, u16 *freq_mhz) | ||
479 | { | ||
480 | int err = 0; | ||
481 | struct nvgpu_clk_arb_target *target; | ||
482 | |||
483 | do { | ||
484 | target = NV_ACCESS_ONCE(session->target); | ||
485 | /* no reordering of this pointer */ | ||
486 | nvgpu_smp_rmb(); | ||
487 | |||
488 | switch (api_domain) { | ||
489 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
490 | *freq_mhz = target->mclk; | ||
491 | break; | ||
492 | |||
493 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
494 | *freq_mhz = target->gpc2clk / 2ULL; | ||
495 | break; | ||
496 | |||
497 | default: | ||
498 | *freq_mhz = 0; | ||
499 | err = -EINVAL; | ||
500 | } | ||
501 | } while (target != NV_ACCESS_ONCE(session->target)); | ||
502 | return err; | ||
503 | } | ||
504 | |||
505 | int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g, | ||
506 | u32 api_domain, u16 *freq_mhz) | ||
507 | { | ||
508 | struct nvgpu_clk_arb *arb = g->clk_arb; | ||
509 | int err = 0; | ||
510 | struct nvgpu_clk_arb_target *actual; | ||
511 | |||
512 | do { | ||
513 | actual = NV_ACCESS_ONCE(arb->actual); | ||
514 | /* no reordering of this pointer */ | ||
515 | nvgpu_smp_rmb(); | ||
516 | |||
517 | switch (api_domain) { | ||
518 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
519 | *freq_mhz = actual->mclk; | ||
520 | break; | ||
521 | |||
522 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
523 | *freq_mhz = actual->gpc2clk / 2ULL; | ||
524 | break; | ||
525 | |||
526 | default: | ||
527 | *freq_mhz = 0; | ||
528 | err = -EINVAL; | ||
529 | } | ||
530 | } while (actual != NV_ACCESS_ONCE(arb->actual)); | ||
531 | return err; | ||
532 | } | ||
533 | |||
534 | int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g, | ||
535 | u32 api_domain, u16 *freq_mhz) | ||
536 | { | ||
537 | switch (api_domain) { | ||
538 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
539 | *freq_mhz = g->ops.clk.measure_freq(g, CTRL_CLK_DOMAIN_MCLK) / | ||
540 | 1000000ULL; | ||
541 | return 0; | ||
542 | |||
543 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
544 | *freq_mhz = g->ops.clk.measure_freq(g, | ||
545 | CTRL_CLK_DOMAIN_GPC2CLK) / 2000000ULL; | ||
546 | return 0; | ||
547 | |||
548 | default: | ||
549 | return -EINVAL; | ||
550 | } | ||
551 | } | ||
552 | |||
553 | int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain, | ||
554 | u16 *min_mhz, u16 *max_mhz) | ||
555 | { | ||
556 | int ret; | ||
557 | |||
558 | switch (api_domain) { | ||
559 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
560 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
561 | CTRL_CLK_DOMAIN_MCLK, min_mhz, max_mhz); | ||
562 | return ret; | ||
563 | |||
564 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
565 | ret = g->ops.clk_arb.get_arbiter_clk_range(g, | ||
566 | CTRL_CLK_DOMAIN_GPC2CLK, min_mhz, max_mhz); | ||
567 | if (!ret) { | ||
568 | *min_mhz /= 2; | ||
569 | *max_mhz /= 2; | ||
570 | } | ||
571 | return ret; | ||
572 | |||
573 | default: | ||
574 | return -EINVAL; | ||
575 | } | ||
576 | } | ||
577 | |||
578 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | 477 | u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) |
579 | { | 478 | { |
580 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | 479 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); |
@@ -589,45 +488,6 @@ u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g) | |||
589 | return api_domains; | 488 | return api_domains; |
590 | } | 489 | } |
591 | 490 | ||
592 | bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain) | ||
593 | { | ||
594 | u32 clk_domains = g->ops.clk_arb.get_arbiter_clk_domains(g); | ||
595 | |||
596 | switch (api_domain) { | ||
597 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
598 | return ((clk_domains & CTRL_CLK_DOMAIN_MCLK) != 0); | ||
599 | |||
600 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
601 | return ((clk_domains & CTRL_CLK_DOMAIN_GPC2CLK) != 0); | ||
602 | |||
603 | default: | ||
604 | return false; | ||
605 | } | ||
606 | } | ||
607 | |||
608 | int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g, | ||
609 | u32 api_domain, u32 *max_points, u16 *fpoints) | ||
610 | { | ||
611 | int err; | ||
612 | u32 i; | ||
613 | |||
614 | switch (api_domain) { | ||
615 | case NVGPU_GPU_CLK_DOMAIN_GPCCLK: | ||
616 | err = clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_GPC2CLK, | ||
617 | max_points, fpoints); | ||
618 | if (err || !fpoints) | ||
619 | return err; | ||
620 | for (i = 0; i < *max_points; i++) | ||
621 | fpoints[i] /= 2; | ||
622 | return 0; | ||
623 | case NVGPU_GPU_CLK_DOMAIN_MCLK: | ||
624 | return clk_domain_get_f_points(g, CTRL_CLK_DOMAIN_MCLK, | ||
625 | max_points, fpoints); | ||
626 | default: | ||
627 | return -EINVAL; | ||
628 | } | ||
629 | } | ||
630 | |||
631 | #ifdef CONFIG_DEBUG_FS | 491 | #ifdef CONFIG_DEBUG_FS |
632 | static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused) | 492 | static int nvgpu_clk_arb_stats_show(struct seq_file *s, void *unused) |
633 | { | 493 | { |
diff --git a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c index e7da0978..b40efc0f 100644 --- a/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c +++ b/drivers/gpu/nvgpu/common/linux/ioctl_ctrl.c | |||
@@ -968,6 +968,20 @@ static int nvgpu_gpu_get_memory_state(struct gk20a *g, | |||
968 | return err; | 968 | return err; |
969 | } | 969 | } |
970 | 970 | ||
971 | static u32 nvgpu_gpu_convert_clk_domain(u32 clk_domain) | ||
972 | { | ||
973 | u32 domain = 0; | ||
974 | |||
975 | if (clk_domain == NVGPU_GPU_CLK_DOMAIN_MCLK) | ||
976 | domain = NVGPU_CLK_DOMAIN_MCLK; | ||
977 | else if (clk_domain == NVGPU_GPU_CLK_DOMAIN_GPCCLK) | ||
978 | domain = NVGPU_CLK_DOMAIN_GPCCLK; | ||
979 | else | ||
980 | domain = NVGPU_CLK_DOMAIN_MAX + 1; | ||
981 | |||
982 | return domain; | ||
983 | } | ||
984 | |||
971 | static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | 985 | static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, |
972 | struct gk20a_ctrl_priv *priv, | 986 | struct gk20a_ctrl_priv *priv, |
973 | struct nvgpu_gpu_clk_vf_points_args *args) | 987 | struct nvgpu_gpu_clk_vf_points_args *args) |
@@ -993,11 +1007,13 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
993 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); | 1007 | clk_domains = nvgpu_clk_arb_get_arbiter_clk_domains(g); |
994 | args->num_entries = 0; | 1008 | args->num_entries = 0; |
995 | 1009 | ||
996 | if (!nvgpu_clk_arb_is_valid_domain(g, args->clk_domain)) | 1010 | if (!nvgpu_clk_arb_is_valid_domain(g, |
1011 | nvgpu_gpu_convert_clk_domain(args->clk_domain))) | ||
997 | return -EINVAL; | 1012 | return -EINVAL; |
998 | 1013 | ||
999 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, | 1014 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, |
1000 | args->clk_domain, &max_points, NULL); | 1015 | nvgpu_gpu_convert_clk_domain(args->clk_domain), |
1016 | &max_points, NULL); | ||
1001 | if (err) | 1017 | if (err) |
1002 | return err; | 1018 | return err; |
1003 | 1019 | ||
@@ -1009,7 +1025,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
1009 | if (args->max_entries < max_points) | 1025 | if (args->max_entries < max_points) |
1010 | return -EINVAL; | 1026 | return -EINVAL; |
1011 | 1027 | ||
1012 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, args->clk_domain, | 1028 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, |
1029 | nvgpu_gpu_convert_clk_domain(args->clk_domain), | ||
1013 | &min_mhz, &max_mhz); | 1030 | &min_mhz, &max_mhz); |
1014 | if (err) | 1031 | if (err) |
1015 | return err; | 1032 | return err; |
@@ -1019,7 +1036,8 @@ static int nvgpu_gpu_clk_get_vf_points(struct gk20a *g, | |||
1019 | return -ENOMEM; | 1036 | return -ENOMEM; |
1020 | 1037 | ||
1021 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, | 1038 | err = nvgpu_clk_arb_get_arbiter_clk_f_points(g, |
1022 | args->clk_domain, &max_points, fpoints); | 1039 | nvgpu_gpu_convert_clk_domain(args->clk_domain), |
1040 | &max_points, fpoints); | ||
1023 | if (err) | 1041 | if (err) |
1024 | goto fail; | 1042 | goto fail; |
1025 | 1043 | ||
@@ -1117,7 +1135,7 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
1117 | 1135 | ||
1118 | clk_range.flags = 0; | 1136 | clk_range.flags = 0; |
1119 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, | 1137 | err = nvgpu_clk_arb_get_arbiter_clk_range(g, |
1120 | clk_range.clk_domain, | 1138 | nvgpu_gpu_convert_clk_domain(clk_range.clk_domain), |
1121 | &min_mhz, &max_mhz); | 1139 | &min_mhz, &max_mhz); |
1122 | clk_range.min_hz = MHZ_TO_HZ(min_mhz); | 1140 | clk_range.min_hz = MHZ_TO_HZ(min_mhz); |
1123 | clk_range.max_hz = MHZ_TO_HZ(max_mhz); | 1141 | clk_range.max_hz = MHZ_TO_HZ(max_mhz); |
@@ -1135,7 +1153,6 @@ static int nvgpu_gpu_clk_get_range(struct gk20a *g, | |||
1135 | return 0; | 1153 | return 0; |
1136 | } | 1154 | } |
1137 | 1155 | ||
1138 | |||
1139 | static int nvgpu_gpu_clk_set_info(struct gk20a *g, | 1156 | static int nvgpu_gpu_clk_set_info(struct gk20a *g, |
1140 | struct gk20a_ctrl_priv *priv, | 1157 | struct gk20a_ctrl_priv *priv, |
1141 | struct nvgpu_gpu_clk_set_info_args *args) | 1158 | struct nvgpu_gpu_clk_set_info_args *args) |
@@ -1167,7 +1184,8 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1167 | if (copy_from_user(&clk_info, entry, sizeof(clk_info))) | 1184 | if (copy_from_user(&clk_info, entry, sizeof(clk_info))) |
1168 | return -EFAULT; | 1185 | return -EFAULT; |
1169 | 1186 | ||
1170 | if (!nvgpu_clk_arb_is_valid_domain(g, clk_info.clk_domain)) | 1187 | if (!nvgpu_clk_arb_is_valid_domain(g, |
1188 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain))) | ||
1171 | return -EINVAL; | 1189 | return -EINVAL; |
1172 | } | 1190 | } |
1173 | 1191 | ||
@@ -1186,7 +1204,7 @@ static int nvgpu_gpu_clk_set_info(struct gk20a *g, | |||
1186 | freq_mhz = HZ_TO_MHZ(clk_info.freq_hz); | 1204 | freq_mhz = HZ_TO_MHZ(clk_info.freq_hz); |
1187 | 1205 | ||
1188 | nvgpu_clk_arb_set_session_target_mhz(session, fd, | 1206 | nvgpu_clk_arb_set_session_target_mhz(session, fd, |
1189 | clk_info.clk_domain, freq_mhz); | 1207 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), freq_mhz); |
1190 | } | 1208 | } |
1191 | 1209 | ||
1192 | ret = nvgpu_clk_arb_commit_request_fd(g, session, fd); | 1210 | ret = nvgpu_clk_arb_commit_request_fd(g, session, fd); |
@@ -1261,15 +1279,18 @@ static int nvgpu_gpu_clk_get_info(struct gk20a *g, | |||
1261 | switch (clk_info.clk_type) { | 1279 | switch (clk_info.clk_type) { |
1262 | case NVGPU_GPU_CLK_TYPE_TARGET: | 1280 | case NVGPU_GPU_CLK_TYPE_TARGET: |
1263 | err = nvgpu_clk_arb_get_session_target_mhz(session, | 1281 | err = nvgpu_clk_arb_get_session_target_mhz(session, |
1264 | clk_info.clk_domain, &freq_mhz); | 1282 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), |
1283 | &freq_mhz); | ||
1265 | break; | 1284 | break; |
1266 | case NVGPU_GPU_CLK_TYPE_ACTUAL: | 1285 | case NVGPU_GPU_CLK_TYPE_ACTUAL: |
1267 | err = nvgpu_clk_arb_get_arbiter_actual_mhz(g, | 1286 | err = nvgpu_clk_arb_get_arbiter_actual_mhz(g, |
1268 | clk_info.clk_domain, &freq_mhz); | 1287 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), |
1288 | &freq_mhz); | ||
1269 | break; | 1289 | break; |
1270 | case NVGPU_GPU_CLK_TYPE_EFFECTIVE: | 1290 | case NVGPU_GPU_CLK_TYPE_EFFECTIVE: |
1271 | err = nvgpu_clk_arb_get_arbiter_effective_mhz(g, | 1291 | err = nvgpu_clk_arb_get_arbiter_effective_mhz(g, |
1272 | clk_info.clk_domain, &freq_mhz); | 1292 | nvgpu_gpu_convert_clk_domain(clk_info.clk_domain), |
1293 | &freq_mhz); | ||
1273 | break; | 1294 | break; |
1274 | default: | 1295 | default: |
1275 | freq_mhz = 0; | 1296 | freq_mhz = 0; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h index 06136c02..e91a0dad 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h +++ b/drivers/gpu/nvgpu/include/nvgpu/clk_arb.h | |||
@@ -102,6 +102,16 @@ struct nvgpu_clk_session; | |||
102 | #define NVGPU_POLLRDNORM (1 << 3) | 102 | #define NVGPU_POLLRDNORM (1 << 3) |
103 | #define NVGPU_POLLHUP (1 << 4) | 103 | #define NVGPU_POLLHUP (1 << 4) |
104 | 104 | ||
105 | /* NVGPU_CLK_DOMAIN_* defines equivalent to NVGPU_GPU_CLK_DOMAIN_* | ||
106 | * defines in uapi header | ||
107 | */ | ||
108 | /* Memory clock */ | ||
109 | #define NVGPU_CLK_DOMAIN_MCLK (0) | ||
110 | /* Main graphics core clock */ | ||
111 | #define NVGPU_CLK_DOMAIN_GPCCLK (1) | ||
112 | |||
113 | #define NVGPU_CLK_DOMAIN_MAX (NVGPU_CLK_DOMAIN_GPCCLK) | ||
114 | |||
105 | #define clk_arb_dbg(g, fmt, args...) \ | 115 | #define clk_arb_dbg(g, fmt, args...) \ |
106 | do { \ | 116 | do { \ |
107 | nvgpu_log(g, gpu_dbg_clk_arb, \ | 117 | nvgpu_log(g, gpu_dbg_clk_arb, \ |